This paper presents a new technique for accurately modeling uni-directional High-Voltage lightly-doped-drain MOS (HV MOS) devices by extending the bi-directional HV MOS model and adopting a new parameter extraction method. We have already reported on a SPICE model for bi-directional HV MOS devices based on BSIM3v3. However, if we apply this bi-directional HV MOS model and its parameter extracti...

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET tech...

As know, a ballistic MOS-Like carbon nanotube FET can be simulated by using a self-consistent procedure between the charge and the Poisson equations. Because of the integral form of the charge equation, this model cannot be implemented in the commercially available circuit simulators, such as SPICE. In this paper, we propose an analytical solution for estimating the charge equation, so that the...

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characterist...

A systematic study of the standard SPICE model of the diode in the case of simulations of power diodes in power electronic applications shows the limits of accuracy with respect to experiments. Therefore, the interest in such a model in power electronic applications is comparable to the high–low resistance model.

This study demonstrates the design and testing of a reconfigurable cascaded time amplifier (TA) that enables a reduction in the output offset. By testing the polarity of the output offset time caused by process variations in each stage and then reconfiguring the inter-stage connections, we find that the total output offset time can be reduced dramatically. The results of a SPICE simulation of a...

A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with...

The 3-SAT problem consists in determining if a boolean formula with 3 literals per clause is satisfiable. When the ratio between the number of clauses and the number of variables increases, a threshold phenomenon is observed: the probability of satisfiability appears in simulations to decrease sharply from 1 to 0 in the neighbourghood of a threshold value, conjectured to be close to 4.25. Altho...

The continuous scaling in transistor dimensions for improving speed and functionality turns device reliability one of the major concerns for nanometer design. This work aims to evaluate the effects of three aging mechanisms acting on the CMOS logic gate reliability for different styles and topologies. Electrical simulations associated to analytical and Spice wearout models are used to compute t...

This paper presents a new general technique for analysis of noise in static log-domain translinear circuits. It is demonstrated that employing this technique, leads to a general, simple and routine method of the noise analysis. . The circuit has been simulated by HSPICE. The simulation results are seen to conform to the theoretical analysis and shows benefits of the proposed circuit. Keywords—N...