Network-on-Chip (NOC) has been proposed as an attractive alternative to traditional dedicated wire to achieve high performance and modularity. Power efficiency is the most important concern in NOC design. Routing algorithms have major effect on power and performance. We have implemented an accurate meshbased hardware model for NOC with VHDL and using it, have measured the performance and power ...

Hierarchical Agent Architecture is proposed to provide online monitoring services to NoC-based systems. Based on circuit conditions traced at the run-time, system settings are monitored adaptively by agents at each architectural level. This monitoring approach partitions various online diagnostic and management services onto hierarchical implementation levels so as to provide scalability and va...

Recent research has shown that Network on-chip (NoC) is superior to a bus in terms of power and area for given traffic throughput requirements. Consequently, NoC is expected to be the main interconnect infrastructure in future System on Chip (SoC) and chip multi-processor (CMP). Unlike off-chip networks, VLSI modules are only a few millimeters apart, hence the cost of off-network communication ...

The el-noc complex spans a distance of about 200 kb on chromosome 2L. It consists of three discrete genetic regions el, l(2)35Ba and noc, each of which has a distinct phenotype when mutant. The noc locus itself is complex, including three separate regions. The el locus has been characterized by mapping 30 aberration breakpoints to the DNA. It extends over a distance of about 80 kb. It can be di...

In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how we approach these limits through a combination of microarchi...

This paper presents a new NoC QoS metrics modeling shaped on mesh architecture. The new QoS model is based on the QoS parameters. The goal of this work is to quantify buffering requirements and packet switching techniques in the NoC nodes by analyzing some QoS metrics such as End-to-End delays (EEDs) and packet loss. This study is based on simulation approach of a 4 × 4 mesh NoC behavior under ...

Chip Multiprocessor Systems (CMPs) rely on a cache coherency protocol to maintain memory access coherence between cached data and main memory. The Hammer coherency protocol is appealing as it eliminates most of the space overhead when compared to a directory protocol. However, it generates much more traffic, thus stressing the NoC and having worse performance in terms of power consumption. When...

To better understand opioid receptor-like 1 (ORL1) internalization, we fused the C terminus of ORL1, the nociceptin (noc) receptor, to the N terminus of a green fluorescent protein and used the fusion protein to characterize receptor endocytosis in live human embryonic kidney cells. The fusion altered neither the affinity of the receptor for noc or other ORL1 receptor ligands nor the ability of...

Network on chip (NOC) architecture is an approach to develop large and complex systems on a single chip. In this work, 2D mesh topological structure has been implemented in Very High Speed Integrated Circuit Hardware Description Language (VHDL). The architecture supports physical and architectural level design integration. Basic communication mechanism between resources is envisioned to be pack...

PURPOSE To investigate the neurotoxic outcome in the rat retina exposed to nitric oxide (NO) released from an NO donor and to evaluate the effects of neurotrophic factors on the survival of NO-damaged retinal cells. METHODS An NO releasing compound, N-ethyl-2-(1-ethyl-2-hydroxy-2-nitrosohydrazino) ethanamine (NOC 12), was intravitreously injected into a rat's right eye. The influences of NOC ...