In this paper, a new strategy of switchable CMOS phase-locked loop frequency synthesizer is proposed to increase its tuning range. The switchable PLL which integrates two phase-locked loops with different tuning frequencies are designed and fabricated in 0.5 μm n-well CMOS process. Cadence/Spectre simulations show that the frequency range of the switchable phased-locked loop is between 320 MHz ...

The study of phase locked loops (PLL) has been heavily treated in literature and most of the theoretical and the analytical results of such are verified using simulations. Here we provide a real-time implementation of a PLL on a digital signal processor (DSP) and analyse and verify the theoretical results associated with it on the implemented system. Such work takes us one step above from the t...

Absfracf-An approach to the implementation of asynchronous and timing jitter insensitive data echo cancellation is described. This approach introduces a small amount of jitter in the transmitted data signal, or alternatively in the received signal sampling, and uses a simple digital phase-locked loop together with the storage of two sets of echo canceler coefficients. The effect of derived timi...

Design and experimental validation of a simple photonic phase-lockedloop (PPLL) linear phase demodulator employing a novel attenuating counter propagating (ACP) in-loop phase modulator are presented. The ACP in-loop phase modulator is free of propagation delay, allowing stable operation of the PPLL with large gain. Highly linear optical phase demodulation was observed and the measured spurious ...

The electronic industry has grown vastly in recent years, and researchers are trying to minimize circuits delay, occupied area and power consumption as much as possible. In this regard, many technologies have been introduced. Quantum Cellular Automata (QCA) is one of the schemes to design nano-scale digital electronic circuits. This technology has high speed and low power consumption, and occup...

This paper presents a quantization noise cancellation technique for frequency-to-digital converter-based fractional-N phase-locked loops (FDC-PLLs). The technique cancels quantization noise prior to the loop filter so the PLL bandwidth can be increased without a significant phase noise penalty. The paper also presents an FDC-PLL architecture enhancement that achieves the effect of a charge pump...

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2 inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of t...

This paper presents a low-complexity real-time single-tone phase and frequency estimation technique based on zero-crossing detection and linear regression. The proposed zerocrossing phase and frequency estimator fills a gap between lowcomplexity phase locked loop estimation and high-performance maximum likelihood estimation. Similar to a phase locked loop, the zero-crossing phase and frequency ...

This paper presents a new circuit for clock generation. A new phase frequency detector is designed in 130nm CMOS process technology. The phase locked loop is designed to meet the 10BaseKR wire line communication standards. All the circuits are designed in current mode logic for high speed operation. The designed circuit dissipates mW. The voltage controlled oscillator has phase noise of -182. 2...

This paper proposes a fast-locking digital delay-locked loop (DLL) with multiphase outputs using mixed-mode-controlled delay line (MCDL). The proposed DLL uses a dual-loop technique to control various MOS capacitors and an MOS resistor in the MCDL to improve locking time and reduce static phase error. The chip was fabricated using a 0.35 μm standard CMOS process with a 3.3 V supply voltage. The...