This brief involves the design and implementation of an energy-efficient and high speed SAR ADC. The DAC would be designed to reduce the power consumption by applying a switching scheme. The architecture of SAR module provides improved speed of conversion. Power consumption is one of the main design constraints in today ICs. For systems that are powered by small non rechargeable batteries over ...

Analog-to-digital converters (ADCs) allow physical signals to be processed using digital hardware. Their conversion consists of two stages: Sampling, which maps a continuous-time signal into discrete-time, and quantization, i.e., representing the continuous-amplitude quantities finite number bits. ADCs typically implement generic uniform mappings that are ignorant task for is acquired, can cost...

A dynamic sampling and digital I/Q-mismatch calibration (IQM) in a MB-OFDM UWB baseband transceiver are proposed to reduce ADC power and analog IQM-calibration power. Measured transceiver power consumes 31.2mW, saving at least 43% ADC power and tolerating 10x IQM (2dB gain and 20 degree phase errors) of existing designs to reduce the power and design efforts from analog calibration circuits.

In the high-resolution analog circuit, performance of chips is an important part. The needs to be determined by testing. According test requirements, stimulus signal with better quality and necessary. main research direction how generate high-speed when there no suitable digital-to-analog converter (DAC) chip available. this paper, we take analog-to-digital (ADC) as example; article uses DAC mu...

An 8-b 650-MHz folding analog-to-digital converter (ADC) with analog error correction in the comparators is presented. With an input frequency of 150 MHz, 7.8 effective bits are obtained. The ADC is implemented in a 1-pm 13-GHz triple-level interconnect bipolar process, requiring 850 mW from a single -4.5-V supply. The die size is 4.2 mm’.

This paper presents a 10-bit, 125 MS/s CMOS pipelined analog-to-digital converter (ADC). The power consumption of this ADC is just 40 mW at a supply voltage of 1.8 V, which is less than half that of other ADCs with an equivalent sampling rate. Low power consumption is achieved by using a flip-around digital-to-analog converter (FADAC) that reduces the power consumption of the front-end circuit ...

In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes less power i n a commercial 90n...

A 7-bit Nyquist folding and interpolating analog-to-digital converter (ADC) that converts at 300 MSamples/s is presented. Using current-mode signal processing techniques for analog preprocessing and a front-end sample-and-hold, the proposed 7-bit folding and interpolating ADC yields a wide input bandwidth up to 60 MHz with six effective number of bits. The ADC consumes 200 mW from a 3.3-V power...

In this paper, we present analysis on the operation and architecture of the voltage controlled oscillator (VCO)based ADC is presented. The VCO-based quantizer is analyzed for two different architectures, one using a frequency-todigital converter (FDC) the other a time-to-digital converter (TDC). The advantages of quantizing the first-stage residue in time domain versus with a voltage domain are...