Optimization-based analog layout automation does not yet find evident acceptance in the industry due to the complexity of the design problem. This paper presents a Self-organized Wiring and Arrangement of Responsive Modules (SWARM), able to consider crucial design constraints both implicitly and explicitly. The flexibility of algorithmic methods and the expert knowledge captured in PCells combi...

Electronic systems designers use FPGAs for their prototype implementations, taking advantage of the devices’ reprogrammability to validate hardware and software. Once the design is ready for volume production, designers are finding that certain types of ASICs—specifically, ASICs with a silicon platform and toolset that enable concurrent design with the FPGA, using identical I/Os, memory resourc...

Introduction and motivation. This work presents results of electrical failure analysis and troubleshooting in an automotive ASIC. An unusual pattern of yield drop-out at sort test occurred suddenly on product which has been in manufacturing for years; no other products were affected by the problem. The pattern indicated strong wafer odd-even effect within a batch with up to 20% yield loss on th...

The Imagine stream processor is a 21 million transistor chip implemented by a collaboration between Stanford Unversity and Texas Instruments in a 1.5V 0.15 μm process with five layers of aluminum metal. The VLSI design, clocking, and verification methodologies for the Imagine processor are presented. These methodologies enabled a small team of graduate students with limited resources to design ...

The process of hardware – software co-design of satellite data acquisition system is described. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes the software tasks. Control of the data flow between device interfaces, processing blocks and memories in a data acquisition system is complex in hardware imp...

In modern designs, voltage drop on the power grid is becoming a critical concern. One important technique to avoid severe voltage drops is to spread the highly power hungry buffers, such as I/O buffers, around the grid. In this paper, we study the problem of I/O buffer placement so as to avoid hot spots which are locations on the chip characterized by high voltage drops. The problem is defined ...

CYCLOPHOSPHAMIDE-INDUCED CYSTITIS REDUCES ASIC CHANNEL, BUT 1 ENHANCES TRPV1 RECEPTOR FUNCTION IN RAT BLADDER SENSORY NEURONS 2 3 Khoa Dang Klaus Bielefeldt and G.F. Gebhart 4 Departments of Pharmacology and Medicine, Carver College of Medicine, The 5 University of Iowa, Iowa City, IA 52242 6 7 8 Running title: Cystitis reduces ASIC but increases TRPV1 function 9 10 11 Author for correspondence...

In this paper we revisit some major orthodoxies which lie at the heart of the bitcoin crypto currency and its numerous clones. In particular we look at The Longest Chain Rule, the monetary supply policies and the exact mechanisms which implement them. We claim that these built-in properties are not as brilliant as they are sometimes claimed. A closer examination reveals that they are closer to ...

VLSI circuits design allows today to consider new modes of implementation for electrical controls. However, design techniques require an adaptation effort that few designers, too accustomed to the software approach, provide. The authors of this article propose to develop a methodology to guide the electrical designers towards optimal performances of control algorithms implementation. Thus, they...

Despite their incentive structure flaws, mining pools account for more than 95% of Bitcoin’s computation power. This paper introduces an attack against mining pools in which a malicious party pays pool members to withhold their solutions from their pool operator. We show that an adversary with a tiny amount of computing power and capital can execute this attack. Smart contracts enforce the mali...