This article describes a defect-oriented test (DOT) approach, which enables complete physical defect-based automatic pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical (TCA)-based methods are presented needed DOT views to enable DOT-based patterns detecting all cell-internal and as well cell-external defects. The major aim these new is further reduce defe...

Static property checking is a technique for verifying some pre-defined design rules such as "bus contention", "racing condition", and "don't-care case". It contains formal verification engines so that a property can be completely verified and if the property is proven false, a counterexample will be generated for debugging the design. Among the different static property checking approaches, ATP...

This tutorial presents a range of design and test techniques and considerations for incorporating high level testability into high performance SOC designs, constructed using embedded cores. Different solutions are proposed around DFT, ATPG and BIST techniques, and their implementation explained from the design and test viewpoints, for different components of SOCs. Capabilities of test automatio...

The increasing complexity of VLSI designs, in recent years, poses serious challenges while ensuring the correctness of large designs for functionality and timing. In this dissertation, we target two related problems in Design Verification and Testing: Unbounded Model Checking and Path Delay Fault Testing, that commonly suffer from extremely large memory requirements. We propose efficient repres...

&VLSI TEST PRINCIPLES and Architectures, edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, is partly a textbook and partly a collection of survey articles on testing by top experts. It works reasonably well in both contexts. Its target audience, according to the preface, includes both students and practitioners. Although this is a noble objective, I don’t think any book can achieve it...

We present an algorithm for computing both functional dependency and unateness of combinational and sequential Boolean functions represented as logic networks. The algorithm uses SAT-based techniques from Combinational Equivalence Checking (CEC) and Automatic Test Pattern Generation (ATPG) to compute the dependency matrix of multi-output Boolean functions. Additionally, the classical dependency...

Modern semiconductor testing is based on the notion of a fault model, that is, the expected behavior (response) of a circuit when a defect is present. ATPG (Automatic test pattern generation) tools use fault models to find the patterns required to detect the presence of defects at all points in the circuit. In part 1 of this series we described the most basic fault models and associated tests: ...

We present a novel test-per-clock BIST method for combinational or full-scan circuits. Our task is to design a combinational circuit, namely the output decoder, transforming the pseudorandom LFSR code words into the required test patterns pre-generated by some ATPG tool. The process is based on finding the coverage of the ones in the test vectors and the subsequent generation of implicants that...

A framework to adaptively perform delay fault diagnosis is introduced. We propose a methodology to perform diagnosis taking into account the effect of test vector on the propagation delay along a path. An ATPG capable of generating test vectors that cannot be invalidated due to process variations in the submicron technology is used for diagnosis purposes. The proposed framework also has the abi...

Process Algebras are a suitable formalism both for system-level description and for ATPG with formal verification techniques. A functional fault model for System-Level descriptions is presented and experimental data are reported. The contributions of this paper are the definition of a general-purpose fault model for concurrently evolving processes and the implementation of a test pattern genera...