In high-performance processors, the accuracy of branch prediction plays a significant role in enhancing computer execution. A new hardware approach is presented in this paper to dynamically predict branch directions using path information. As an execution path contains large information, we compress the large information using a technique based on the linear feedback shift register (LFSR) that ...

We consider the filter generator over GF (2) consisting of a linear feedback shift register of length k that generates a maximal length linear sequence of period 2 − 1 over GF (2) and a Boolean function of degree d that combines bits from one element in the shift register (considered as an element in GF (2)) and creates a binary output bit zt at any time t. We show how to extend a recent attack...

A modified Linear Feedback Shift Register is designed in which power consumption reduction by deactivating the clock signal to Flip Flop when the output signal is same as input signal. The power consumption of the new LFSR is reduced due to the reduced switching of Flip Flop To verify, the maximum, minimum and average

This work presents a 24 Gb/s pseudo random bit sequence (PRBS) generator with a sequence length of 2 − 1 . The circuit uses an interleaved linear feedback shift register and multiplexing architecture. An output voltage swing of 280 mVpp is achieved for 24 Gb/s data rate and 390 mVpp for 10 Gb/s. The circuit features a trigger output which allows to trigger the eye or the sequence pattern. The c...

Let a be an l-sequence generated by a feedback-with-carry shift register with connection integer q = pe, where p is an odd prime and e 1. Goresky and Klapper conjectured that when pe = 2 f5; 9; 11; 13g, all decimations of a are cyclically distinct. When e = 1 and p > 13, they showed that the set of distinct decimations is large and, in some cases, all deciamtions are distinct. In this article, ...

A new lossless test vector compressionn scheme is presentedd whichh combines linear feedback shift register (LFSR) reseedingg andd statistical codingg inn aa powerful way. Test vectors cann be encodedd as LFSR seeds by solvingg aa system of linear equations. The solutionn space of the linear equations cann be quite large. The proposedd methodd takes advantage of this large solutionn space too f...

In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit format and implemented using field programmable gate array (FPGA). The design of the RISC is facilitated like basic signals sine, cosine, square, modulation schemes amplitude modulation, shift keying, analog, digital quadrature modulation. Ad...

For any integer N > 1, we construct feedback with carry shift registers over Z/(N) (N -FCSRs). The case when N is a prime, was investigated by Klapper and Goresky [1, 2]. We present the basic properties of N -FCSRs. We solve the register synthesis problem: given a small number of symbols of a sequence over Z/(N) synthesize the smallest N -FCSR that outputs the sequence.