A parallel adder which is optimal in both delay and size under left-to-right input arrival is proposed. The delay is the computation time after the arrival of the nal input bits. The proposed adder is composed of a carry select adder (CSA) and a small adder based on the on-they conversion (OTFA). Parallel computation in the CSA and the OTFA which make full use of the delay of the input arrival ...

A representation changer is a function that converts a concrete representation of an abstract value into a different concrete representation of that value. Many useful functions can be recognised as representation changers; examples include compilers, and arithmetic functions such as addition and multiplication. Functions that can be specified as the right inverse of other functions are special...

All reversible circuits have an intrinsic advantage over traditional irreversible circuits, because the reduce power consumption. Due to this, reversible circuits have been a source of constant excitement and great enthusiasm in the scientific community. Reversible logic is highly useful in nanotechnology, low power design and quantum computing. This paper proposes a design for a faster adder u...

This paper proposes an architecture for implementing a self-checking 4-bit carry select adder that can be extended to any n-bit addition. The overhead is directly proportional to the number of transistors in the adder.

We present the design of a quantum carry-lookahead adder using measurement-based quantum computation. The quantum carry-lookahead adder (QCLA) is faster than a quantum ripple-carry adder; QCLA has logarithmic depth while ripple adders have linear depth. Our design is evaluated in terms of number of time steps and the total number of qubits used.

Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI technique. GDI technique is power efficient technique for designing digital circuit that consumes less power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum propagation delay, minimum area required and less complexity for designing any digital circuit. We desi...

Adder being the basic hardware block of any arithmetic operation, the major constraint in the field of signal processors, data processors to perform any operations are highly dependent on the adder performance of the circuit. The gate level implementation of the carry select adder (CSLA) and modified carry select adder has significantly reduced the area and power consumption which replaced the ...

Parallel-prefix adders (also known as carrytree adders) are known to have the best performance in VLSI designs compared to that of conventional Ripple Carry Adder (RCA). However, each type of parallel prefix adder has its own pros and cons and are chosen according to the design requirement of the application. This paper investigates mainly two types of carry-tree adders, the brent kungg adder a...