Hewlett-Packard University Memorial Auditorium, August 8-10, 1993. In the five years since its inception, the annual symposium has grown into one of the most popular and fun conferences for chip designers, architects, and users, The informal atmosphere at the beautiful Stanford University campus in late summer, coupled with technical presentations on the latest “product-oriented” chips, seem to...

Defective chips may pass structural tests applied via scan chains (also called test escapes). We conducted many experiments on test chips fabricated in three different technologies (0.13μm, 0.18μm, and 0.35μm) to understand the extent of the number of test escapes and to develop techniques that minimize the number of test escapes. This paper presents the test chips, the setup of the experiments...

The microstructures of copper chips created by plane strain machining at ambient temperature have been analyzed using transmission electron microscopy (TEM) and orientation imaging microscopy (OIM). The strain imposed in the chips was varied by changing the tool rake angle. Characterization of orthogonal faces of the chips showed the microstructure to be essentially uniform through the chip vol...

Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI...

Let $a$, $b$, and $n$ be integers with $0<a<b<n$. In a certain two-player probabilistic chip-collecting game, Alice tosses coin to determine whether she collects $a$ chips or $b$ chips. If chips, then Bob vice versa. A player is announced the winner when they have accumulated number of that multiple $n$. this paper, we settle two conjectures from literature related game.