We examined influence of a clock ticking on task performance using a laboratory experiment. We determined performance at various clock speeds using a trick clock that allowed us to control the speed of the ticking. We found that which the clock ticked, and people performed more slowly with a slow clock. We demonstrated that common environmental stimuli we encounter in life, such as the ticking ...

Low power chip requirement in the VLSI industry is main considerable field due to the reduction of chip dimension day by day and environmental factors. In this paper various low power techniques at Gate level, Architecture level and different tradeoffs between different clock distribution schemes like as single driver clock scheme and distributed buffers clock scheme are reviewed. Here it is al...

Recent measures to reduce Medicare spending include the use of competitive bidding in determining reimbursement prices. Several competitive bidding experiments have been conducted by the Centers for Medicare and Medicaid Services (CMS) to determine reimbursement prices. This paper investigates the use of competitive bidding to set reimbursement prices for durable medical equipment, prosthetics,...

Virtually all animals have endogenous clock mechanisms that "entrain" to the light-dark (LD) cycle and synchronize psychophysiological functions to optimal times for exploring resources and avoiding dangers in the environment. Such circadian rhythms are vital to human mental health, but it is unknown whether circadian rhythms "entrained" to the LD cycle can be overridden by entrainment to daily...

Multinational corporations have IT departments that span the globe to support distributed business ventures. IT staff must provide support for the information systems that these centers of operations depend on, round the clock and around the globe. This provides an opportunity to study the phenomenon of distributed IT support team. This study examined how a distributed IT support team coordinat...

Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A methodology for enhancing the layout of the clock tree to reduce the uncertainty of the clock signal is presented in this paper. The primary objective of the proposed methodology ...

A clock generation technique for reducing the clockjitter sensitivity of Switched current (SI) Return-to-Zero (RZ) DAC in CT ΣΔ modulators is presented in this paper. While realizing the clock-jitter insensitivity, this technique ensures that the feedback period can be utilized more efficiently so that the amplitude of feedback current can be reduced. The proposed technique employs simple digit...