CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future under sub 10 nm regime, because of the enhanced carrier transport properties [1-4]. Here, there can be several CMOS structures using III-V/Ge channels, as schematically shown in Fig. 1. While one of the ultimate CMOS structures...

Several CMOS-MEMS tunable capacitors have been designed, fabricated and tested. Large-tuning ranges and high Q values are achieved. The structures were made from the CMOS interconnect stack using a maskless CMOS micromachining process. The 1 generation capacitors were fabricated using Austria Microsystems (AMS) 0.6 μm and Agilent 0.5 μm CMOS process. These devices have a measured nominal capaci...

*1: CDS: Correlated double sampling CMOS sensors are now widely used in cellular phones and other mobile devices, and as a result, sales of these devices have been increasing rapidly. Furthermore, demand for CMOS sensors has been increasing in fields that require high-speed imaging functions, such as digital singlelens reflex cameras. While CMOS sensor advantages over CCD include lower power co...

This paper describes an on-chip series-regulated mixed swing methodology with sleep-mode control for lowering the power consumption of high-performance DSP multiplier-accumulator (MAC) circuits. A 16*16+36-bit Overlapped bit-pair Booth recoded, Wallace tree MAC is fabricated in a commercial 0.5μm CMOS process in the proposed series-regulated methodology and conventional static CMOS. Up to 2.55X...

We describe a novel biochemical sensing method and its potential new biosensing applications. A light-sensitive complementary metal oxide semiconductor (CMOS) chip prepared through a standard 0.5m CMOS process was developed for measuring biochemical reactions. A light producing enzymatic reaction catalyzed by horseradish peroxidase (HRP) was designed as a platform reaction to determine the conc...

This paper reports a lateral CMOS-MEMS accelerometer with a measured noise floor of 1mG/ and a dynamic range larger than 13G. The accelerometer is fully compatible with conventional CMOS processes enabling the integration of most of the conditioning circuits. It is fabricated in a three metal layer 0.5μm CMOS process followed by a two-step dry etch release. An improved curl matching technique i...

The research of the last ten years has resulted in the attempts towards single chip CMOS RF circuits for Bluetooth, ISM and DECT applications. An overvieuw of the use of CMOS for low-cost integration of a high-end cellular RF transceiver front-end is presented. Some fundamental pitfalls and limitations of RF CMOS are discussed. To circumvent these obstacles the choice of transceiver architectur...

This paper gives important features of CMOS and BiCMOS four-diodes direct coupled tuneable resistance. Circuit performances of three resistance topologies are explored and compared with the traditional CMOS tuneable transresistance designed from a one-stage operational transconductance amplifier (OTA). Simulations results have been realised using nominal parameters of the AMS 0.8μm CMOS and BiC...

In this paper we present an ultra low-voltage and high speed D flip-flop. The flip-flop has an increased current level compared to standard CMOS circuits operating at low supply voltages. The increased current level is obtained by using a synchronized capacitive coupling to a semi floating-gate. The delay of the static differential flip-flop presented is less than 12% compared to conventional d...

Abstract--We have proposed, in this paper a, TCAD/DA methodology for MPU and ASIC with updated processes and devises, which allow a predictive chip-design with quick quantitative correlation studies between process-recipe and CKT & delay parameters required in DA works. Effects of statistical process variation on 0.35um CMOS have been rigorously characterized with a new global TCAD calibration ...