The advantages of fully-depleted (FD) SOI CMOS technology in comparison to bulk Si regarding analogue circuit design have been reported in [1]. Most of them relate to the combination of the reduced capacitance of SOI technology with the better transconductance (gm) over drain current (IDS) ratio due to the reduced FD body factor, which provides enhanced bandwidth and gain, resulting in very sig...

5 ASIC Technologies 8 5.1 Full Custom Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Standard Cell ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Gate Array ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Sea-of-Gates ASIC Technology . . . . . . . . . . . ....

This paper describes the construction and analysis of several diagrams which depict SRT division al orithms. These diagrams yield insight into the operation of the algorithms and the many imp ementation tradeoffs available in custom circuit desi n. B radix diagrams are shown, as well as tables for higher radices. Ig Examples of simple low he tables were enerated by a program which can create an...

Based on the ASIC layout level simulation of 7 types of adder structures each of four different sizes, i.e. a total of 28 adders, we propose expressions for the width of each of the three regions of the final Carry Propagate Adder (CPA) to be used in parallel multipliers. We also propose the types of adders to be used in each region that would lead to the optimal performance of the hybrid final...

In this paper, we propose the first method for post-silicon customization of resource binding for low power application specific integrated circuits (ASICs) design. We devise and implement a new synthesis framework that generates a diverse set of resource binding candidates where any one of the candidates could be selected post-silicon. Orthogonal arrays are used to construct multiple candidate...

A novel analogue power-efficient 2-D programmable finite impulse response image filter is proposed. This solution is based on the current-mode Gilbert-vector-multiplier operating in the weak inversion region, which allows for ultra low power operation. The main advantage is in the asynchronous and parallel calculation of all pixel values without using any clock generator. The filter is a progra...

A versatile precision rectifier based on a current conveyor and current mirrors is presented. The proposed circuit performs positive half-wave, negative half-wave, positive full-wave, and negative full-wave rectification into a single circuit. The current-mode technique has been employed to provide the high-precision capability of the circuit. The circuit configuration is very suitable for inte...

This paper illustrates the design of low-power, high-performance SR flip-flop. The speedy technical trends are engrossing to decrease the geometrical feature size and power consumption of the integrated circuit in VLSI designs. The proposed design shows the comparison with conventional CMOS circuit on the basis of power consumption and propagation delay and can save up to a significant amount o...

Technology development and continuous down scaling in CMOS fabrication makes Mixed Signal Integrated Circuits (MSIC) more vulnerable to process variation. This paper presents a well defined novel design methodology for process variability aware design by incorporating the major challenge of statistical circuit performance relating the device and circuit level variation in an accurate and effici...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.