Metrics of energy, area, and time are defined Cor a graphthe<>retic model of \'LSI computation. Different "constant factors" are se1'n to. be appropriate for different logic families. We ex amine seven such familie!l: NMOS, CMOS, CMOS-SOS, J2L, Gru\s liEMT, JJ-CrL, and JJ-CS. For each family, we sketch a construction f6r an energy-efficient, read/write, random-access memory circuit.

Abstract CMOS processes that have been developed primarily for logic are now increasingly used for analog and mixed signal applications. Process restrictions, wide parametric variance, and noisy application environments lead to special efforts in circuit design/architecture, layout techniques, and optimizing the use of a limited process. This paper addresses a combination of techniques that pro...

The single flux quantum (SFQ) logic family is a novel digital as it provides ultrafast and energy-efficient circuits. For large-scale SFQ circuit design, specialized electronic design automation (EDA) tools are required due to the differences in type, timing constraints, architecture, contrast Complementary metal–oxide–semiconductor (CMOS) logic. In order improve overall performance of an circu...

CMOS is used to construct the integrated circuits with low level of static leakage. With this low level leakage we are designing all the transistor circuits in CMOS logic. To control this static leakage in the circuits the supply voltage is a major concern. Here the step-up converters with charge pump and the level for maintaining its threshold voltage (VT) is to be analyzed and proposed. Here ...

This paper describes a semi-dynamic CMOS flip-flop family featuring embedded Threshold Logic functions. First, we present the concept of flip-flop featuring embedded Threshold Logic, and then we describe the circuit and its operation. Subsequently, we present the design issues and the experimental results of such Threshold Logic flip-flops, obtained in 0.25pm CMOS technology. It is shown in thi...

The objective of this embedded tutorial is to give an overview for the state of the art of the pass-transistor logic technologies and their future prospects. The talk gives a survey summary for recent researches and developments on the pass-transistor logic technologies based on more than 100 surveyed papers that have been published after 1983. The number of publications has been rapidly increa...

An Energy Efficient Feedthrough Logic (EE-FTL) is proposed in this paper to reduce the power consumption for low power applications. The EE-FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. It has a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. The proposed logic style ...

This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft error on the internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from particle hit on combinational logic. The proposed circuit has low power consumption with negative se...

Noise in digital logic circuits does not reduce with the scaling down of CMOS devices. The conventional CMOS design does not provide noise immunity when the circuits are operated in the sub threshold region. In order to enhance the performance of the circuit and to handle the errors caused due to noise that are random and dynamic in nature, a cost effective probabilistic based noise tolerant ci...