Design of a new sense amplifier-based flip-flop (SAFF) using GDI Technique and performance comparison of proposed SAFF with existing conventional SAFF with CMOS-NAND latch SAFF and SAFF with CMOS Symmetric latch is presented in this paper. It was found that the main drawback of existing SAFF’s is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output sta...

This paper describes a straightforward methodology for ultra low power design of a radiofrequency building block in CMOS technology. This design methodology is based on two parameters: First, the inversion coefficient of the transistor and the extracted equations from the radiofrequency circuits. Second, an optimum tradeoff between the performance key parameters such power consumption, gain, no...

Design and operation of high-gain (>1000), low-power (< 75 jtW), ultra low-noise amplifier arrays are presented. The amplifier array is operated in self-biased mode, such that all amplifiers are biased irrespective of threshold mismatches, and operate with low reset noise. The amplifiers are designed for possible incorporation as pixels of hybrid solid-state photon-counting sensor. The cell pit...

A novel class-AB transconductance amplifier, suitable for the input stage of high slew rate CMOS operational amplifier is proposed. The proposed class-AB transconductor is realized from a differential pair of mixed translinear common-drain push-pull circuit. A high speed operational amplifier employing the proposed input stage and a complementary common –source high gain stage is presented. HSP...

the graphical technique for nonlinear circuits was described that enable us to optimize circuits to obtain maximum output power, maximum efficiency or minimum intermodulation. according to this method a high power amplifier in the ka band was designed. using a nonlinear model of the transistor, optimum slope for load-line was determined so that maximum power at the output was obtainable, then ...

A key issue in the design of biomedical implants is the design of low-power area-efficient circuits that allow for highdensity neural recording. This paper presents an ultra low-power (<1.4μW ), area efficient low-noise neural amplifier that utilizes current-feedback miller-compensation technique and occupies <0.08mm silicon area. Integrating the large input capacitor within the electrodes save...

This paper presents a ultra wideband low noise amplifier for 6GHz Applications. This proposed LNA is the extension of inductively common source amplifier and in this design we used transistor multifingering techniques in order to reduce noise and improves gain. This LNA is simulated by using UMC .18um CMOS mixed signal/RF process in cadence virtuoso. In this design, used current source biasing,...

This paper presents the design and realization of low power, high gain PC based system for ECG and data acquisition of a patient’s heart condition. The advantage of this system is the use of standard CMOS process which will reduce the complexity and cost of the manufacturer. The system consists of three subsystemsOperational Amplifier based Pre-amplifier, ADC and USB interface device. High gain...

This paper describes the design of Current Mode Instrumentation Amplifier (CMIA) for ECG signal Acquisition system. The CMIA topology is based on voltage mode operational amplifier (op-amp) power supply current sensing technique. Op amp mismatch and precise current mirrors are two design challenges of this topology. High Common Mode Rejection Ratio (CMRR) and Power Supply Rejection Ratio PSRR i...

This paper presents a low-power linear variable gain amplifier (VGA). This VGA gains its low-power linear properties with the help of the local feedback auxiliary (LFA) amplifier. The core of this LFA amplifier is based on flipped voltage follower (FVF) circuit. This VGA provides the flexibility to tune its gain with dual tuning voltages. Gain range of 15 dB to 16 dB with maximum bandwidth of 2...