Shweta Jain Department of Computer Applications, Shri R.G.P. Gujarati Professional Institute, Indore-10 Email: [email protected] Dr. Saurabh Jain Institute of Computer Applications, Shri Vaishnav Vidyapeeth Vishwavidyalaya, Indore Email: [email protected] ----------------------------------------------------------------------ABSTRACT--------------------------------------------------------...

Computation-in-Memory (CIM) is an emerging computing paradigm to address memory bottleneck challenges in computer architecture. A CIM unit cannot fully replace a general-purpose processor. Still, it significantly reduces the amount of data transfer between traditional and processor by enriching transferred information. Data transactions consist access addresses values. While main focus field in...

  The traveling salesman problem is a well-known and important combinatorial optimization problem. The goal of this problem is to find the shortest Hamiltonian path that visits each city in a given list exactly once and then returns to the starting city. In this paper, for the first time, the shortest Hamiltonian path is achieved for 1071 Iranian cities. For solving this large-scale problem, tw...

A large register set can be exploited by keeping variables and constants in registers instead of in memory. Hardware register windows and compiletime or link-time global register allocation are ways to do this. A measure of the effectiveness of any of these register management schemes is how thoroughly they manage to remove loads and stores. This measure also must count extra loads and stores t...

An algorithm for integrating instruction scheduling and register allocation must support mechanisms for detecting excessive register and functional unit demands and applying reductions for lessening these demands. The excessive demands for functional units can be detected by identifying the instructions that can execute in parallel, and can be reduced by scheduling some of these instructions se...

Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this paper, we propose an integrated power management approach that unifies low level architectural optimizations(CPU, memory, register), OS power-saving mechanisms (Dynamic Voltage Scaling) and adaptive middleware techniques(admission control, optimal transcoding, network tra...

In a modern computer, the CPU operates on values in its registers, and can fetch values from main memory, usually via several layers of caches. Large files are stored on disk, and data is transferred from disk to main memory. The memory closest to the CPU is fastest but smallest, and the memory farthest from the CPU is largest but has the highest latency. Moreover, the slower layers of memory h...

The perception of modal and falsetto registers was analyzed in a material consisting of a total of 80 vowel sounds sung by 10 choir singers, 40 sung in modal register and 40 in falsetto register. These vowel sounds were classified by sixteen expert listeners in a force choice test and the number of votes for modal was compared with the voice source parameters (1) Closed Quotient (Qclosed)and (2...

In a modern computer, the CPU operates on values in its registers, and can fetch values from main memory, usually via several layers of caches. Large files are stored on disk, and data is transferred from disk to main memory. The memory closest to the CPU is fastest but smallest, and the memory farthest from the CPU is largest but has the highest latency. Moreover, the slower layers of memory h...

Register renaming is a widely used technique to remove false data dependencies in superscalar datapaths. Rename logic consists of a table that holds a physical register mapping for each architectural register and a logic for checking intra-group dependencies. This logic checking consists of a number of comparators that compares the values of destination and source registers. Previous research h...