The primary objective of the Multimedia Router (MMR) project is the design and implementation of a compact router optimized for multimedia applications. The router is targeted for use in cluster and LAN interconnection networks, which offer different constraints and therefore differing router solutions than WANs. The goal is to provide architectural support to enable a range of Quality Of Servi...

As the number of transistors on a single chip increases rapidly, there is a productivity gap between the increasing number of available transistors and the design time. One solution to reduce this productivity gap is to increase the reusability of Intellectual Property (IP) cores. However, an IP core should be customized/configured before being used in a system different than the one for which ...

This paper explores theories on designing optimal multipoint interconnection structures, and proposes a simple switch box design scheme which can be directly applied to field programmable gate arrays (FPGAs), switch box designs, and communication switching network designs. We present a new hyperuniversal switch box designs with four sides and terminals on each side, which is routable for every ...

This paper presents and evaluates distributed queueing algorithms for regulating the flow of traffic through large, high performance routers. Distributed queueing has a similar objective to crossbar-scheduling mechanisms used in routers with relatively small port counts, and shares some common high level characteristics. However, the need to minimize communication overhead rules out the iterati...

Shared memory architecture for packet switches was normally thought to be unsuitable for building high performance switches/routers. The main reason lies in their perceived poor scalability. In particular, shared memory architectures are typically used to build output-queued switches which are regarded as the best candidate to achieve optimal delay-throughput performance. The current trend in r...

Conventional rigid and generalpurpose on-chip networks occupy significant logic and wire resources in fieldprogrammable gate arrays (FPGAs). To reduce the area cost, the authors present a topology customisation technique, using which on-demand network interconnects are systematically established in reconfigurable hardware. First, the authors present a design of a customised crossbar switch, whe...

Absfracf-A new scheduling algorithm that concatenates data blocks to increase switching throughput is proposed. The algorithm controls the degree of concatenation and reduces the number of switching instances to improve switch utilization. The switch architecture uses a virtual output queue switching architecture where the core switch fabric is an optical matrix switch. The optical matrix switc...

Architectures based on a non-blocking fabric, such as a crosspoint switch, are attractive for use in high-speed LAN switches, IP routers, and ATM switches. These fabrics, coupled with memory bandwidth limitations, dictate that queues be placed at the input of the switch. But it is well known that input-queueing can lead to low throughput, and does not allow the control of latency through the sw...

State of the arts on guided-wave optical switch arrays are reviewed. In this paper, electro-optic Ti:LiNbO3 devices are mainly described in comparison with crosspoint switch element structures and switch array architectures. Packaging technologies and stability problems are discussed for practical system applications. Recent development on other materials such as semiconductor waveguides, therm...