A new measuring instrument for 10 points soil temperatures in 0~50 centimeters depth underground was designed. System was based on Silicon Laboratories’ MCU C8051F310, single chip digital temperature sensor DS18B20, and other peripheral circuits. It was simultaneously able to measure, memory and display, and also convey data to computer via a standard RS232 interface.

ChIP-Seq technology, which combines chromatin immunoprecipitation (ChIP) with massively parallel sequencing, is rapidly replacing ChIP-on-chip for the genome-wide identification of transcription factor binding events. Identifying bound regions from the large number of sequence tags produced by ChIP-Seq is a challenging task. Here, we present GLITR (GLobal Identifier of Target Regions), which ac...

Mapping the chromosomal locations of transcription factors, nucleosomes, histone modifications, chromatin remodeling enzymes, chaperones, and polymerases is one of the key tasks of modern biology, as evidenced by the Encyclopedia of DNA Elements (ENCODE) Project. To this end, chromatin immunoprecipitation followed by high-throughput sequencing (ChIP-seq) is the standard methodology. Mapping suc...

While microprocessor pipeline depths have increased dramatically over the last decade, they are fast approaching their optimal depth. As shown in Figure 9.6.1, the number of logic levels in modern processors is nearing 10 fanoutof-4 (FO4) inverter delay. Substantial further reductions will be undesirable due to pipeline overheads and power consumption [1]. Technology trends also show that globa...

The built up layer thickness in secondary deformation zone is one of the important parameters in metal cutting process. The built up layer (BUL) is formed in second deformation zone near the tool-chip interface in the back of the chip. This parameter influences the tool life and machined surface quality. This BUL should not be confused with the built up edge (BUE). The deformation of the BUL in...

The complexity in the hardware implementation of traditional optical code-division multiple-access correlation receivers with double optical hardlimiters is discussed. A comparison with the implementation of recently proposed chip-level receivers is presented as well. In addition, the bit error probabilities and the throughput capacities for both chip-level and correlation systems (without hard...

In this paper we describe the principles of the chip multiprocessor architecture, overview design alternatives and present some example processors of this type. We discuss the results of several simulations where chip multiprocessor was compared to other advanced processor architectures including superscalars and simultaneous multithreading processors. Although simultaneous multithreading seems...

Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level ...

Actor-oriented modeling approaches are convenient for implementing functional models of embedded systems. Architectural models for heterogeneous system-on-chip architectures, however, are usually implemented using transaction level modeling (TLM). Even though both modeling paradigms, actor-oriented design and TLM, can conveniently be implemented using a common language such as SystemC, a method...

as technology scales deep into the nanometer regime, on-chip communication becomes more susceptible to transient noise sources, such as crosstalk, external radiation, and spurious voltage spikes. the network on chip s modularity and reusability has brought about the use of error control methods to address transient errors in network on chip links.in this work, we design a fault tolerance router...