In this paper a new area efficient, high-speed and ultra-low power 1-bit full adder cell is presented. The performance: power, time delay and power delay product (PDP) of the proposed adder cell has been analyzed in comparison with the four existent low-power, high-speed adders. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology and intensive simul...

This article presents the design of a new asynchronous early output full adder which when cascaded leads to a relative-timed ripple carry adder (RCA). The relative-timed RCA requires imposing a very small relative-timing assumption to overcome the problem of gate orphans associated with internal carry propagation. The relative-timing assumption is however independent of the RCA size. The primar...

In this paper, a new logiedesign style called Pseudo Dynamic Logic (SDL) is introduced. In this logiedesign style, the internal nodes of the logic circuits are not precharged to high or low values, rather the initial charges on nodes are shared to yield an intermediate precharge value for faster evaluation. A 32-bit adder has been designed and simulated using HSPICE Level-49 parameters of a 0 ....

Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It o...

The novel design of various adiabatic adders based on pass transistor logic is introduced. Also, a new I-bit full adder basic cell with a small number of transistors is designed. The architectural design of each adiabatic adder and new formulas for their corresponding delay, are presented. The performance of various adiabatic adders, in this work, against the performance of theirs CMOS counterp...

This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC flow, tools used during factors to consider maximize performance ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part all processors. In this study, two ALUs were implemented using types adder circuits: Ripple Carry Adder (RCA) Sklansky adder. Ca...

Adder trees are the crucial design blocks of many arithmetic VLSI circuits. Alternative implementations can solve the large area requirements and complicated interconnection scheme of these building blocks. Multiple Valued Logic (MVL) implementation of an adder tree can be an alternative design style, which can save from area and interconnect.

The two different architectures for adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of modulo 2n+1 addition. This sparse approach is enabled by the introduction of inverted circular idem potency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by th...

-This paper explains a new approach to design Exclusive-OR gate using 2 transistors. A full adder circuit has been designed by using proposed 2T Exclusive-OR circuit and a transmission gate is used extensively in very large-scale integration (VLSI) application. The power dissipation of the adder is in range of 421.7256uw to 581.542uw in 0.35 um technology with a voltage supply is in the range o...