— Living cells generate the cell cycle or apoptosis, depending on the course will be repeated. If an error occurs during this period of life in order to maintain the cells in the peripheral cells find the error portion. These cellular functions were applied to the system to simulate the circuit. Circuit implementation of the present study was constructed the redundant structure in order to foun...

The digital PWM modulator circuit is capable of varying the duty cycle of the output (PWM) according to the digital input word. A digitally controlled current starved pulse width modulator is described. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the r...

SABYASACHI CHAKRABORTY Sr. Lecturer and Head of the Department Department of Computer Science /IT Icfai University-Sikkim. Sikkim, India. Abstract— In this paper first the traditional digital to analog conversion is discussed with circuit analysis. The concepts like propagation delay, inertial delay, step size are discussed. In the later part, the fuzzy logic circuit interface between digital t...

In long pulse discharge tokamak, a large number of diagnostic channels are being used to understand the complex behavior of plasma. Different diagnostics demand different types of analog and digital processing for plasma parameters measurement. This leads to variable requirements of signal processing for diagnostic measurement. For such types of requirements, we have developed hardware with rec...

Due to aggressive scaling and process imperfection in sub-45 nm technology node Vt (threshold voltage) shift is more pronounced causing large variations in circuit response. Therefore, this paper presents the analyses of various popular 1-bit digital summing circuits in light of PVT (process, voltage and temperature) variations to verify their functionality and robustness. The investigation is ...

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental ...

Unfortunately there are some problems in deIn this paper, we present a n e f i c i e n t and accurate’ IDDQ faul t modeling technique f o r digital CMOS circuit. Both, the normal and faul ty “current” behaviors of a CMOS digital circuit can be described by th i s model. Also the parasit ic capacitive and induct ive parameters can be emulaled. A f o r m a l method f o r creating this model f r o...

An LDMOS RF high power amplifier with improved intermodulation distortion performance using digital predistortion is presented. The application of digital linearization method is being tested with the help of circuit simulation software ADS.

The Central Pattern Generator (CPG) model proposed by Matsuoka is widely used by various robots. It consists of several differential equations. However, unlike some other CPG models that have been realized by analog circuits, Matsuoka’s CPG model is usually solved by analytical methods (such as Runge-Kutta method) on digital processors. This may require great computational power, especially whe...

As current computer-aided design (CAD) tool and very large scale integration technology capabilities create a new market of reusable digital designs, the economic viability of this new core-based design paradigm is pending on the development of techniques for intellectual property protection. This work presents the first technique that leverages the unique characteristics of fieldprogrammable g...