The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterog...

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In the past signal processing algorithms for mobile communications systems were implemented in hardware using a single chip solution, usually a Digital Signal Processor (DSP). But due to the increased and still increasing complexity of these signal processing algorithms, the computational power of single chip solutions is not sufficient any more. In addition the number of algorithms to be proce...

The hybrid amplifier that combines a buck converter and linear has been widely used as the envelope tracking (ET) supply modulator for ET power (PA) application. Instead of adding more large off-chip passives to raise efficiency amplifier, this work uses Viterbi-like trellis search (TS) digital signal processing (DSP) algorithm find optimal switching sequence in lowering RMS error current op-am...

Sigma-Delta ( ) modulation has become a popular technique for achieving high resolution in modern A/D and D/A converters. On-chip test techniques for this type of circuits have been made available recently in the literature. These techniques are based on measuring parameters such as signal-to-noise ratio (SNR) and harmonic and intermodulation distortion. However, they require considerable on-ch...

Most scientific and digital signal processing (DSP) applications are recursive or iterative. The execution of these applications on a chip multiprocessor (CMP) encounters two challenges. First, as most of the digital signal processing applications are both computation intensive and data intensive, an inefficient scheduling scheme may generate huge amount of Write operation, cost a lot of time, ...

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Prog...

This is a technical and experimental report of parallel processing, using the "Propeller" chip. Its eight 32 bits processors (cogs) can operate simultaneously, either independently or cooperatively, sharing common resources through a central hub. I introduce this unique processor and discuss about the possibility to develop interactive systems and smart interfaces in media arts, because we need...

Silicon technology has now advanced to the point that there is a serious mismatch in the time taken to design advanced silicon-based systems and the time to market for any new product or product derivative. To obviate this delay, a new paradigm is emerging based on intellectual property (IP) exchange, where designers and differing companies share subsystems (virtual cores) between themselves to...

SPRY061 System developers, especially those who are new to digital signal processors (DSPs), are sometimes uncertain whether they need to use fixedor floating-point DSPs for their systems. Both fixedand floating-point DSPs are designed to perform the highspeed computations that underlie real-time signal processing. Both feature system-ona-chip (SOC) integration with on-chip memory and a variety...