Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-toanalog converters (DACs). The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise. This paper describes an all-digital technique that significantly mitigates this problem. The tec...

At BESSY the standard 16 bit resolution of the corrector power supplies was insufficient for the continuous orbit drift correction [1]. A new sophisticated design of the analog/digital I/O board [3] increases the resolution of the analog output up to 24 bits without suffering on losses in the long term stability or the dynamic range of the correctors. This is achieved by a cost-efficient board ...

This paper describes a new firstand second-order delta-sigma modulator concept where the first integrator is extracted and implemented by a frequency modulator with the modulating signal as the input. The result is a simple delta-sigma modulator with no need for digital-to-analog converters, allowing straight-forward multi-bit quantization. Without the frequency modulator, the circuit becomes a...

With the increased sophistication of System-on-Chip (SOC) architectures comes an increased need for low power Analog to Digital converters. These converters have many uses including Built-in-Self-Test (BIST) applications. In this paper, we present a novel Successive Approximation ADC. We show how one can utilize an existing DAC structure on an SOC to realize an effective Analog-to-Digital conve...

Two architectures for a 1-V, 10-bit 200-kS/s successive approximation analog-to-digital converter (ADC) implemented in a standard CMOS 0.18 μm digital process are presented. A track-andhold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch with a novel rail-to-rail trackand-latch comparator circuit is described. A pMOS-only ladder containing a rail-to-ra...