This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme for dynamic circuits provides the solution of the problem caused by logic polarity and clock skew problem simultaneously. To demonstrate the proposed clocking strategy, a 32 bit Carry Look Ahead adder (CLA) is designed a...

Dynamic Bayesian networks (DBN) are handy tools to model complex dynamical systems learned from collected data and expert knowledge. However, expert knowledge may be incomplete, and data may be scarce (this is typically the case in Life Sciences). In such cases, using precise parameters to describe the network does not faithfully account for our lack of information. This is why we propose, in t...

Experiments at storage ring light sources as well as at next-generation light sources increasingly require detectors capable of high dynamic range operation, combining low-noise detection of single photons with large pixel well depth. XFEL sources in particular provide pulse intensities sufficiently high that a purely photon-counting approach is impractical. The High Dynamic Range Pixel Array D...

The fast development in the fields of integrated circuits, photovoltaics, the automobile industry, advanced manufacturing, and astronomy have led to the importance and necessity of quickly and accurately obtaining three-dimensional (3D) shape data of specular surfaces for quality control and function evaluation. Owing to the advantages of a large dynamic range, non-contact operation, full-field...

High dynamic range images must be tone mapped before being displayed on devices with low output dynamic range. Two existing global tone mapping operators are evaluated and then a new improved operator using a sigmoid compression curve is proposed. It is then demonstrated through simulation and experimental results that an existing capture device, used previously only for simple logarithmic comp...

In order for dynamic circuits to operate correctly, their inputs must be mono-tonically rising during evaluation. Blocking dynamic circuits satisfy this constraint by delaying evaluation until all inputs have been properly setup relative to the evaluation clock. By viewing dynamic gates as latches, we demonstrate that the optimal delay of a blocking dynamic gate may occur when the setup time is...

This study aimed at the implementation and synchronization control of cardiac circuit. First, the MATLAB-Simulink was used to simulate the dynamic behavior of cardiac chaotic circuit, and simple electronic modules were used to implement the cardiac system. Then the Particle Swarm Optimization PSO was used to seek for the proportional, integral, and derivative gains of optimal PID controller, an...

In any VLSI circuit, power consumption is very important factor that should be taken into consideration. Generally, dynamic power consumption is more dominant when compared to that of static. To reduce the internal switching activity rate of the circuit under test (CUT), we can recombine testing vector to raise the correlation between testing vector. Random Single Input Change (RSIC) test theor...

An analog QRS complex detection circuit, for pacemaker applications, based on the Wavelet Transform (WT) is presented. The system detects the wavelet modulus maxima of the QRS complex. It consists of a wavelet transform filter, an absolute value circuit, a peak detector and a comparator. In order to achieve the low-power requirement in pacemakers, we propose a new method for implementing the WT...

Previous work in leakage current reduction for digital circuits can be divided into two main categories: static design-time selection of slow, low-leakage transistors for non-critical paths and dynamic deactivation of fast leaky transistors on critical paths. Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors could potentially yield large savings. W...