In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an...

Evolutionary algorithms (EAs) are regularly used both for the solution of scheduling problems, and for the creation of digital circuit designs. This paper describes a unified approach, which mixes the creation of a sequential circuit, with the scheduling and binding of operations. This paper describes how Finite Impulse Response Primitive Operator Filters (FIR POFs) can be created so that they ...

The paper presents an evolutionary approach to the design of fault-tolerant VLSI (very large scale integrated) circuits using EHW (evolvable hardware). The EHW research area comprises a set of applications where GA (genetic algorithm) are used for the automatic synthesis and adaptation of electronic circuits. EHW is particularly suitable for applications requiring changes in task requirements a...

The application of evolution-inspired strategies to hardware design and circuit self-con-guration leads to the concept of evolvable hardware (EHW). EHW refers to self-con-guration of electronic hardware by evolutionary/genetic algorithms (EA and GA, respectively). Unconventional circuits, for which there are no textbook design guidelines, are particularly appealing for EHW. Here we applied an e...

In the last five years, the field of evolutionary computation (EC) has seen a resurgence of new ideas, many stemming from new biological inspirations. This paper outlines four of these new branches of research: Creative Evolutionary Systems, Computational Embryology, Evolvable Hardware and Artificial Immune Systems, showing how they aim to extend the capabilities of EC. Recent, unpublished resu...

Reconfigurable embedded systems are nowadays widely used, since they have the capability to modify their functionalities, adding or removing components and modify interconnections among them. In this work, the main emphasis will be on the definition of a framework, based on reconfigurable architecture, where hardware components can autonomously evolve to define the best system characterization ...

We analyze and compare four different evolvable hardware approaches for classification tasks: An approach based on a programmable logic array architecture, an approach based on two-phase incremental evolution, a generic logic architecture with automatic definition of building blocks, and a specialized coarse-grained architecture with pre-defined building blocks. We base the comparison on a comm...

The paper proposes an on-line evolvable hardware (EHW), called mimetic EHW. The task is to mimic a sequential circuit by observing its partial input/output sequences. The genetic algorithm (GA) is used to search for the circuit satisfying input/output sequences collected from the target circuit. The mimetic EHW consists of a custom microprocessor and a tness evaluator. The microprocessor is par...

This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to congure a scalable neural network hardware system. In our system, both the topology and the hidden layer node functions of a neural network mapped on the chips are dynamically changed using a genetic algorithm. Thus, the most desirabl...

In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable system is based on the implementation of a search algorithm in the PowerPC processor which is available in Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Candidate filters are evaluated in a domain-specific virtual reconfigurable circuit implemented using a reconfigurable logic of the s...