A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage. The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.

This work presents a campaign of fault injection to validate the dependability of a fault tolerant microcomputer system. The system is duplex with cold stand-by sparing, parity detection and a watchdog timer. The faults have been injected on a chip-level VHDL model, using an injection tool designed with this purpose. We have carried out a set of injection experiments (with 3000 injections each)...

This paper addresses the problem of estimating the coverage of a fault tolerance mechanism through statistical processing of observations collected in fault-injection experiments. In an earlier paper, several techniques for sampling the fault/activity input space of a fault tolerance mechanism were presented. Various estimators based on simple sampling in the whole space and stratified sampling...

The paper assesses the effectiveness of the Circular Self-Test Path BIST technique from an experimental point of view and proposes an algorithm to overcome the low fault coverage that often arises when real circuits are examined. Several fault simulation experiments have been performed on the ISCAS89 benchmark set, as well as on a set of industrial circuits: in contrast to the theoretical analy...

The use of multiple voltage settings for dynamic power management is an effective design technique. Recent research has shown that testing for resistive bridging faults in such designs requires more than one voltage setting for 100% fault coverage; however switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes an effective gat...

ÐThis paper addresses the problem of estimating fault tolerance coverage through statistical processing of observations collected in fault-injection experiments. In an earlier paper, various estimators based on simple sampling in the complete fault/activity input space and stratified sampling in a partitioned space were studied; frequentist confidence limits were derived based on a normal appro...

Coverage-based fault localization techniques assess the extent of how much a program entity relates to faults by contrasting the execution spectra of passed executions and failed executions. However, previous studies show that different test cases may generate similar or identical coverage information in program execution, which makes the execution spectra of program entities indistinguishable ...

One of the important features of digital instrumentation and control (I&C) systems is the faulttolerant technique. Fault-tolerance is the system’s capability to help the system perform correctly the specific required functions in spite of the presence of faults. In the fault tolerance evaluation, fault detection coverage is a crucial factor. The fault detection coverage is the ability to detect...

With the progression from large scale integration (LSI) to very large scale integration (VLSI), and eventually ultra large scale integration (ULSI), integrated circuit fault coverage is becoming increasingly important. Naturally as we move from LSI towards ULSI the area consumed by devices is getting ever larger. Larger area devices are known to have a higher probability of containing manufactu...

In earlier research we developed a theory for predicting the reliability of conventional sequential programs based on an estimate of residual faults. This paper describes how the theory was applied to a realistic industrial example containing a known number of faults. The industrial example was implemented in a PLC application language where the program is represented by a network of logic gate...