In nature, localization is a very fundamental task for which natural evolution has come up with many powerful solutions. In technical applications, however, localization is still quite a challenge, since most ready-to-use systems are not satisfactory in terms of costs, resolution, and effective range. This paper proposes a new localization system that is largely inspired by auditory system of t...

This paper begins with a short discussion of the basic concepts of reconfigurable computing. Configuration is the process of programming a field-programmable gate array (FPGA) device for implementing a certain logic function. Configuration can be either static or dynamic. In static configuration the FPGA device retains its configuration state till the task is completed. In dynamic configuration...

This paper discusses design and testing of a Moving Picture Experts Group 2 (MPEG-2) Transport Stream (TS) multiplexer in Field Programmable Gate Array (FPGA) technology that would transmit multiplexed packets via Ethernet. Multiplexer is designed in accordance with standard ISO/ IEC 13818-1, thus it is fully compatible with standard players. The digital design is very flexible since adding add...

In the development and commercialization phase of information technology products implemented as a system on a chip (SoC), field-programmable gate array (FPGA) based platform has been widely used as the logic function test methodology for basic or advanced features and mobile station emulator. In this situation, to define the uniform verification approach on FPGA development platform, we introd...

1 A tool has been created for use in a design course to automate integration of new components into a SystemOn-Chip (SoC). Students used this tool to implement a complete SoC Internet firewall, which was prototyped and tested using a field-programmable gate array (FPGA). Common components of the framework were completed as machine problem assignments throughout the first half of the semester. D...

This paper describes ongoing work involving the use of the X i l i n x X C 6 2 1 6 r a p i d l y reconfigurable field-programmable gate array to evolve sorting n e t w o r k s u s i n g g e n e t i c programming. We successfully evolved a network for sorting seven items that employs two fewer steps than the sorting network described in a l962 patent and that has the same number of steps as the ...

This paper describes experiments to determine how the architecture vis-a-vis routing and functional resources affect the ease with which combinational logic designs may be evolved on a field-programmable gate array (FPGA). We compare two chromosome representations with differing levels of connectivity, and show that the amount of routing and functional resource have a marked effect on the succe...

We propose and demonstrate an Ethernet transport system that can support hard real-time traffics with guaranteed throughput and very low jitter performance even in the presence of asynchronous traffics. The superframe structure-based Ethernet system first synchronizes all the nodes in a network by using the IEEE 1588-compliant boundary clock scheme and then reserves the traffic channels for syn...

In this paper, a novel field programmable analog arrays (FPAA) architecture, namely, NueroFPAA, is introduced to utilize nanodevices to build a programmable neuromorphic system. By using nanodevices as programmable components, the proposed FPAA can achieve high-density and low-power operations for neuromorphic applications. The routing and function blocks of the FPAA are specifically designed s...