Hardware validation and verification studies for emulator circuits of the memristor element usually include either analog or digital realization results. In this study, implementation stages a using Joglekar window function with programmable reconfigurable platforms are given together in order to observe characteristic current–voltage relationship, experimentally. Herein, function-based voltage...

This article proposes an efficient design and implementation of Framelet-Based Orthogonal Frequency Division Multiplexing (OFDM) with Finite Radon Transform (FRAT), named as (FRAT-FTOFDM), on Field Programmable Gate Array (FPGA) platform. Modern FPGA design tool called Xilinx System Generator (XSG) is used to implement the transceiver of FRAT-FT-OFDM system. The FPGA implementation is carried o...

The division of a monolithic neural network into blocks with their implementation on programmable logic within the framework Fog computing concept is considered. It assumed that considering possible reconfiguration performed logic: field-programmable gate array, FPGA (complex device, CPLD), System-on-a-Chip, SoC or System-in-Package, SiP. article explores such an in Proteus Design Suite based A...

Interleaving along with error correction coding is an effective way to deal with different types of error in digital data communication. Error burst due to multipath fading and from other sources in a digital channel may be effectively combated by interleaving technique. In this paper an efficient technique to model convolutional interleaver using a hardware description language is proposed and...

The succesful application of model predictive control (MPC) in fast embedded systems relies on faster and more energy efficient ways of solving complex optimization problems. A custom quadratic programming (QP) solver implementation on a field-programmable gate array (FPGA) can provide substantial acceleration by exploiting the parallelism inherent in some optimization algorithms, apart from pr...

In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or field-programmable gate array (FPGA) prototyping board. This work presents FPGA that takes ladder diagram (LD) control for PLC and converts to Verilog HDL programs such the board is used real application. We explor...

Due to their Shannon-limit-approaching performance and low-complexity decoding, low-density parity-check (LDPC) codes have been used for forward error correction in a broad-range of communication and storage systems. In addition to its low-complexity, the iterative decoding algorithm used for decoding LDPC codes is inherently parallel. To exploit the parallelism at a larger extent, a significan...

In recent years there has been a great interest in accelerating time consuming algorithms that solve large combinatorial optimization problems [1]. The advent of high density field programmable gate arrays in combination with efficient synthesis tools have enabled the production of custom machines for such difficult problems. Genetic Algorithms (GAs) [13] are robust techniques based on natural ...

In this paper, we propose the hardware implementation of involutional block ciphers with low energy cost for cryptographic algorithm to WSNs by FPGA implementation. Formerly, microcontroller based sensor nodes are designed like PIC microcontroller, AT Mega128 microcontroller, MSP430.But it have some drawbacks .1) High processing time2) It consumes large amount of energy3) It have less security4...