An industry standard 8'' silicon-on-insulator wafer based ultra-thin (1 μm), ultra-light-weight, fully flexible and remarkably transparent state-of-the-art non-planar three dimensional (3D) FinFET is shown. Introduced by Intel Corporation in 2011 as the most advanced transistor architecture, it reveals sub-20 nm features and the highest performance ever reported for a flexible transistor.

This paper deals with the propagation delay comparison of half adder with different FETs; such as MOSFET, CNTFET, FINFET. Nanotechnology is the promising field which functions at the molecular level to replace the conventional use of classical CMOS. By simulation, the best part is got that CNTFET shows lesser delay for half adder circuit.

The constant pace of CMOS technology scaling has enabled continuous improvement in integrated-circuit cost and functionality, generating a new paradigm shift towards mobile computing. However, as the MOSFET dimensions are scaled below 30nm, electrostatic integrity and device variability become harder to control, degrading circuit performance. In order to overcome these issues, device engineers ...

Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power Sherif A. Tawfik1 ∗ and Volkan Kursun2 1Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin, USA 2Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Clear Water Bay, Kowlo...

This paper reviews recent approaches in the development of a tunable work function metal gate CMOS technology and describes the application of one such approach to the fabrication of metal gate fullydepleted (FD) SOI transistor structures such as the ultra-thin body (UTB) FET and the FinFET.

Fast and accurate reliability estimation of integrated circuits is an open problem. Introducing the emerging nano devices such as FinFET and Stacked Silicon nanowires makes this problem even more challenging because of higher lithography fluctuation. We discuss several previous efforts for reliable circuit design and propose a methodology for accurate reliability estimation of novel transistors.