This is a preliminary study in which we use a genetic algorithm (GA) to breed normalized postfix expressions for solving the facility layout problem (FLP). Our technique, initially developed for VLSI floorplanning, simultaneously places rectangles onto a planar site and optimizes area utilization by altering the shapes of facilities that have fixed area but flexible height and width dimensions....

Research in layout design during the past decade has had a significant impact on the entire VLSl industry. Because of advances made in automatic placement and routing, application specific integrated circuit (ASIC) design now represents a sizeable portion of the chip market. The influence of computer-aided physical design will continue to be felt in the future; for example, in further populariz...

This paper presents a novel layout model and floorplanning tool particularly suitable for taking into account user defined layout constraints on specific sets of modules and specific locations. The user defined layout constraints can be the setting of any common topological property associated with a group of specific modules such as the neighboring property for example. Or the use of any topol...

Systems-on-Chip (SoCs) and Chip Multiprocessors (CMPs) have strong global communication requirements, and networks-on-chip (NoCs) have been proposed as a scalable solution to overcome these communication challenges. This work explores the application of NoCs in both SoCs and CMPs. For SoCs, our work considers the application-specific NoC architecture design problem in a 3D environment. We prese...

As System-on-Chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this technical report, we address this problem by prop...

Field Programmable Gate Arrays (FPGA) have become an alternative to traditional Digital Signal Processors (DSP) in many applications. In some cases, where high throughput is the main concern, an FPGA-based system may in fact be the only solution to fulfil the requirements. In the area of particle accelerators, FPGAs are used in many contexts, ranging from digital feedback loops for power conver...

Run-time reconfiguration of FPGAs has been around in academia for more than two decades but it is still applied very seldom in industrial applications. This has two main reasons: a lack of killer applications that substantially benefit from run-time reconfiguration and design tools that permit to quickly implement corresponding reconfigurable systems. This tutorial gives a survey on state-of-th...

achieves the searching not only globally, but also locally. To keep general purpose, self-control processing by a handshake system is introduced. By adopting the handshake system, the proposed architecture can be applied to various combinatorial optimization problems by only changing an encoder, a decoder, and an evaluation circuit. Furthermore, the proposed architecture realizes flexibility fo...

This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic partitioning, floorplanning, global routing, and timing analysis/budgeting steps, followed by technology remapping and detailed placement of the selected logic clusters. The strength of the approach lies in the dynamic programming...

Repeaters are widely used to combat the quadratic delay of long on-chip wires. A conventional repeater is a CMOS inverter placed periodically along the long wire. This design has two drawbacks. The wire must have an even number of repeaters to preserve signal polarity. This forces the designer to sometimes use a suboptimal number of repeaters. It is also awkward when a wire branches because rep...