System on chip (SOC) design integrates many complex modules in one chip. As number of modules per chip is increasing, number of transistors in a chip increases resulting in increase in area and power dissipation. Area and power dissipation problems can be most effectively addressed if the basic building blocks of the circuit are designed for lower power dissipation and occupy less space. Flip-F...

Neuronal activity can rapidly flip-flop between stable states. Although these semi-stable states can be generated through interactions of neuronal networks, it is now known that they can also occur in vivo through intrinsic ionic currents.

Flip-Flop_1: Firstly, the old flip-flop construction that we choose to implement is the classic single edge triggered flip-flop (SETFF) which is shown in FIGURE 10.24 in the book " CMOS VLSI Design A Circuits and Systems Perspective " 4th Edition. The figure is shown below. Fig A-1 Resettable Flip-Flop The schematic that we construct is shown as follows: Fig A-2 Resettable Flip-Flop Schematic T...

-This paper proposes a low-power and area-efficient shift register using digital pulsed latches. The area and power consumption are reduced by replacing flip-flops with pulsed latches. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. The shift register uses a ...

We present a new automatic test pattern generation algorithm for sequential circuits by traversing the partitioned state spaces. The new features include: (1) nondisjoint state groups are obtained such that two different state groups may have common flip-flops, (2) partial state transition graphs (STGs) are constructed at run time for each state group, (3) spectral information for state variabl...

Flip-flops is critical timing elements in digital circuits which have a large impact on the circuit speed and power consumption. The performance of flip-flop is an important element to determine the efficiency of the whole synchronous circuit . In an attempt to reduce power consumption in flip-flops a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a mod...