The methodology for the design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented in this paper. Basic principles of partial dynamic reconfiguration are described together with their impact on the fault tolerance features of the digital design implemented into the SRAM-based FPGA. The methodology includes detection ...

All rights reserved by www.ijsrd.com 535 FPGA to PC Ethernet Communication using Media Independent Interface (MII) Mode Preeti Kumari Sidharth Kashyap Ajit Jain Lokesh Sharma Department of Electronics Engineering CDAC Noida, GGSIPU Delhi Abstract— As the advancement in the embedded system technology, Field programmable gate array (FPGA) based systems are playing significant role. In many applic...

This paper aims at demonstrating the whole process allowing implementing a robust in-system update solution for Microblaze-based embedded systems using low-cost and low-power consuming Spartan-6 FPGA. In this work, we design a run-time full reconfigurable embedded platform based on the Spartan-6 Multiboot and fallback features. The FPGA Multiboot feature enables switching between two or more co...

ÐThe speed of arithmetic calculations in configurable hardware is limited by carry propagation, even with the dedicated hardware found in recent FPGAs. This paper proposes and evaluates an approach called delayed addition that reduces the carrypropagation bottleneck and improves the performance of arithmetic calculations. Our approach employs the idea used in Wallace trees to store the results ...

Las Funciones Físicamente No-Clonables (PUF) basadas en osciladores de anillo (RO-PUF) son una las implementaciones PUF FPGA más utilizadas actualmente. Sin embargo, la arquitectura afecta a aleatoriedad respuesta. En este trabajo, proponemos algunas formas optimizar RO-PUF implementada FPGA.

Balancing the use of FGPA resources such as FPGA slices, block RAMs, and block multipliers is desirable in many FPGA applications. This task can be carried out manually by experienced hardware designers with the use of hardware description languages, such as Verilog and VHDL. However, many users of reconfigurable computers are software developers who depend on hardware synthesis tools or even h...

This paper presents an alternative approach for dynamic partial self-reconfiguration that enables a Field Programmable Gate Array (FPGA) to reconfigure itself dynamically and partially through a parallel configuration access port (PCAP) under the control of the stand alone PCAP core within the FPGA instead of using an embedded processor. The reconfiguration process is accomplished without an in...

The principle, configuration, and the special features of an infrared imaging system are presented in this paper. The work has been done in two parts. First, the nonuniformity of IRFPA is detected using a processing system based on FPGA & microcontroller. The FPGA generates system timing and performs data acquisition, while the microcontroller reads the IRFPA data from FPGA and sends them to th...