This paper gives the comparison of performance of full adder design in terms of area, power and delay in different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more number of transistors compared to GDI. GDI occupies less area compared to all other l...

In the recent years reversible logic design has promising applications in low power computing, optical computing, quantum computing. VLSI design mainly concentrates on low power logic circuit design. In the present scenario researchers have made implementations of reversible logic gates in optical domain for its low energy consumption and high speed. This study is all about designing a reversib...

1 Associate Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India. 2 Assistant Professor, Department of Electronics and Communication Engineering, Nalla Narasimha Reddy Group of Institutions, Hyderabad, Telangana, India ---------------------------------------------------------------------***------------------...

Diverse advanced logic circuits are fabricated to implement arithmetic functions based on a simple and single molecular beacon platform, including half adder, half subtractor, full adder, full subtractor, and a digital comparator. Dual fluorescence outputs are generated in parallel and a constant threshold value is set to build all the logic circuits. The developed enzyme-free DNA system provid...

In this paper Modified Booth Multiplier (radix-4) implemented by various adder. Partial product generated by booth encoder is added by various adder techniques to compare the performance parameter of multiplier. Performance parameter like area, path delay, fan out, speed of multiplier. Multiplication is an important fundamental function in arithmetic logic operation. Since, multiplication domin...

Transistor makes up the cornerstone of modern computing. In this work, a SPICE model GNRFET was used to simulate performance NMOS and CMOS binary full adder. The adder evaluated in terms its average power consumption propagation delay. Three variables, namely resistance value, dimer lines channel length were manipulated impact on assessed. It observed that linear improvement delay accompanied b...