The work described in this paper is performed to estimate the influence of statistical process variations and transistor mismatch that occurs in fabrication and affect floating-gate digital circuits. These effects will affect and reduce “yield” (percentage of fully functional circuits). Monte Carlo simulations have been performed in a 90 nm to estimate the yield for manufactured floating-gate c...

nano-crystalline Si dots of dimensions of 8nm have been incorporated into a variety of Coulomb blockade and floating gate memory devices. Structures include vertical transistor, planar electrode, nanoscale channel junction and 2-gate trench structure. Ballistic transport, Coulomb oscillation and memory effects are clearly demonstrated

An area efficient technique for tuning floatinggate circuits is described. The effective threshold voltage seen from a control gate can be programmed to virtually any value. The floating-gate transistor (FGMOS) may be used to implement low-power/low-voltage digital -and/or analog circuits.

In order to calculate ion currents through solid-state nanopore transistors realistically, we propose a computational model based on the Poisson-Nernst-Plank equation. In the present model, we determine the surface charge density locally on the nanopore by imposing consistency between the ion distribution and the chemical reaction at the surface. The model can consider a non-uniform influence b...

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a si...

We describe the design, fabrication, characterization, and modeling of an array of single transistor synapses. The single transistor synapses simultaneously perform long term weight storage, compute the product of the input and oating gate value, and update the weight value according to a hebbian or a backpropagation learning rule. The charge on the oating gate is decreased by hot electron inje...

Atomic layer deposition ALD grown Al2O3 has excellent bulk and interface properties on III-V compound semiconductors and is used as gate dielectric for GaAs and GaN metal-oxide-semiconductor field-effect transistors MOSFETs . The low-temperature LT ALD technology enables us to fabricate 100 nm MOS structures on GaAs, defined by nanoimprint lithography. The electrical characterization of these n...

Continued miniaturization of bulk silicon CMOS transistors is being limited by degrading short channel effects. Traditionally, higher channel doping, shallower source/drain junctions, and thinner gate dielectrics have been employed to improve gate control and enhance performance as the gate length is scaled down. However, these techniques are rapidly approaching material and process limits. Alt...

The next generation of electronics is likely to incorporate various functional materials, including those exhibiting ferroelectricity, ferromagnetism and metal-insulator transitions. Metal-insulator transitions can be controlled by electron doping, and so incorporating such a material in transistor channels will enable us to significantly modulate transistor current. However, such gate-controll...

This paper reviews recent approaches in the development of a tunable work function metal gate CMOS technology and describes the application of one such approach to the fabrication of metal gate fullydepleted (FD) SOI transistor structures such as the ultra-thin body (UTB) FET and the FinFET.