In a diagram editor, one can distinguish initial from incremental diagram layout. The former computes a diagram layout from scratch, whereas the latter adjusts an existing layout after diagram modifications. In previous work, we have proposed a pattern-based approach as a solution for incremental diagram layout in visual language editors. Each LP encapsulates certain layout behavior. A diagram’...

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on int...

Elevators are the essential transportation tools in high buildings so that elevator group control system (EGCS) is developed to dynamically layout the schedule of elevators in a group. In this study, a fuzzy rule based intelligent EGCS optimized by genetic algorithm has been proposed where the rules with the corresponding parameters are generated optimally so as to maximize service quality. The...

In this paper, a quaternion firefly algorithm is utilized to solve a multi-row facility layout design problem with the objective of minimizing the total cost of transportation. A quaternion firefly algorithm takes the motion of the firefly as a quaternion one. Consequently, the solution space is explored more accurately and the answers are of higher quality. That is, the answers are considerabl...

Objective: In this paper, a conceptual framework for integrating production scheduling in flowshop manufacturing cells, known as group (FSGSP), and unequal-area facility layout (UAFLP) decisions is proposed. Materials Methods: First, brief literature review carried out to identify the elements, solution techniques complementary UAFLP, FSGSP layout-scheduling approaches. Results: Based on result...

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on int...