This paper elucidates the system construct of DA-FIR filter optimized for design distributed arithmetic (DA) finite impulse response (FIR) and is based on architecture with tightly coupled co-processor data processing units. With a series look-up-table (LUT) accesses in order to emulate multiply accumulate operations constructed DA FIR implemented FPGA. The very high speed integrated circuit ha...

This doctoral thesis deals with designing residue number system based building blocks to enhance the performance of digital signal processing applications. The residue number system (RNS) is a non-weighted number system that provides carry-free, parallel, high speed, secure and fault tolerant arithmetic operations. These features make it very attractive to be used in high-performance and fault ...

An efficient architecture of 1D CSDA MST core is designed using CSDA (Common Sharing Distributed Arithmetic) to achieve high-throughput rate supporting multistandard transformations at low cost. Common sharing distributed arithmetic (CSDA) combines factor sharing and distributed arithmetic sharing techniques, efficiently reducing the number of adders for high hardware-sharing capability. Conven...

waterwheels are the oldest types of hydraulic machines. these turbines are of relatively simple design, large diameter, low rotational speed and high torques. but applying them as micro hydros of high speed and small diameter is yet to be explored. a micro hydro waterwheel of one meter diameter was designed and manufactured at the iranian  esearc†h organization for science and technology (irost...

   Multiplier is one of the important components in many systems such as digital filters, digital processors and data encryption. Improving the speed and area of multipliers have impact on the performance of larger arithmetic circuits that are part of them. Wallace algorithm is one of the most famous architectures that uses a tree of half adders and full adders to increase the speed and red...