A Phase Locked Loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2Gbit/s-3Gbit/s range ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25u CMOS pr...

This paper proposes an active capacitive sensing circuit for fingerprint sensors, which includes a pixel level charge-sharing and charge pump to replace an ADC. This paper also proposes the operating algorithm for 16-level gray scale image. The active capacitive technology is more flexible and can be adjusted to adapt to a wide range of different skin types and environments. The proposed novel ...

This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural models were designed to implement the 53-bit mantissa path of the IEEE standard 754 for floating point multiplication, and tested for functionality in Verilog. The design, which was done in dual-rail domino, was simulated ...

A novel voltage-mode multifunction biquadratic filter with one input and six outputs is presented. The proposed circuit can realize inverting and noninverting low-pass, bandpass, and high-pass filters, simultaneously, by using two inverting second-generation current conveyors (ICCIIs), two grounded capacitors, and four resistors. Moreover, the proposed circuit offers the following attractive ad...

A modeling study of dynamic threshold voltage in high K gate stack is reported in this paper. Both slow transient (STCE) and fast transient charging effect (FTCE) are included in this model. Finally, this model is applied in FinFET reliability and circuit performances are simulated. The result shows that, the drain circuit (Id) degradation in FinFET is much more obvious than normal MOSFETs with...

Analytical methods for gate delay estimation are very useful to speedup timing analysis of digital integrated circuits. This work presents a novel approach to analytically estimate the CMOS inverter delay. The proposed method considers the influence of input slope, output load and I/O coupling capacitance, as well as relevant effects such as channel length modulation and drain induced barrier l...

Non zero signal rise and fall times contribute significantly to CMOS gate performances such as propagation delay or short circuit power dissipation. We present a closed form expression to model output rise and fall times in deep submicron CMOS structures. The model is first developed for inverters considering fast and slow input ramp conditions. It is then extended to gates through a reduction ...

For deep-submicron, high-performance circuits, the inductive effect plays a very important role in determining the circuit delay. In this paper, we derive accurate formulae for modeling the delays of buffered RLY/RLC wires and trees. Our formulae can handle balanced and un-balanced trees and consider buffer insertion. Extensive simulations with HSPICE show that the formulae have high fidelity, ...

Development of large computerized systems requires both combinational and sequential circuits. Registers and counters are two important examples of sequential circuits, which are widely used in practical applications like CPUs. The basic element of sequential logic is Flip-Flop, which stores an input value and returns two outputs (Q and Q ). This paper presents an innovative ternary D Flip-Flap...

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number high-impedance nodes, frequency compensation has biggest challenge in design multistage amplifiers. The new technique this study uses two differential stages to organize feedforward feedback paths. Five Miller loops a 500-pF load capacitor are driven by just tiny com...