Instruction caches consume a large fraction of the total power in modern low-power microprocessors. In particular, set-associative caches, which are preferred because of lower miss rates, require greater access energy on hits than direct-mapped caches; this is because of the need to locate instructions in one of several ways. Way prediction has been proposed to reduce power dissipation in conve...

In this paper we present a Branch Target Bu er BTB design for energy savings in set associative in struction caches We extend the functionality of a BTB by caching way predictions in addition to branch target addresses Way prediction and branch target prediction are done in parallel Instruction cache energy savings are achieved by accessing one cache way if the way pre diction for a fetch is av...

The wide spread adoption of the internet as a trusted medium of communication and commerce has made cryptography an essential component of modern information systems. So the performance of cryptographic communication applications on network processor has become an important topic of network processor system design. In this paper I compare and analyze the architectural characteristics of some wi...

Recent research results show that conventional hardware-only cache solutions result in unsatisfactory cache utilization for both regular and irregular applications. To overcome this problem, a number of architectures introduce instruction hints to assist cache replacement. For example, Intel Itanium architecture augments memory accessing instructions with cache hints to distinguish data that wi...

Spin Transfer Torque RAM (STT-RAM) is a form of computer data storage which allows data items to read and write faster. Every peripheral circuit have some static power consumption, which is consumed while there is no circuit activity. The main objective of the paper is to reduce the static power consumption in peripheral circuits with the help of STT-RAM technology. Instead of fetching instruct...

In this paper, we present our design for a high performance prefetcher, which exploits various localities in both local cache-miss streams (misses generated from the same instruction) and the global cache-miss address stream (the misses from different instructions). Besides the stride and context localities that have been exploited in previous work, we identify new data localities and incorpora...

Java has, in recent years, become fairly popular as a platform for commercial servers. However, the behavior of Java server applications has not been studied extensively. We characterize two multithreaded Java server benchmarks, SPECjbb2000 and VolanoMark 2.1.2, on two IBM PowerPC architectures, the RS64-III and the POWER3-II, and compare them to more traditional workloads as represented by sel...

In this paper we propose Instruction-based Prediction as a means to optimize directory-based cache coherent NUMA shared-memory. Instruction-based prediction is based on observing the behavior of load and store instructions in relation to coherent events and predicting their future behavior. Although this technique is well established in the uniprocessor world it has not been widely applied for ...

Cache memory is a common structure in computer system and has an important role in microprocessor performance. The design of a cache is an optimization problem that is mainly related with the maximization of the hit ratio and the minimization of the access time. Some aspects related with the cache performance are the cache size, associativity, number of words per block and latency. In this pape...

Java has become fairly popular on commercial servers in recent years. However, the behavior of Java server applications has not been studied extensively. We characterize two Java server benchmarks, SPECjbb2000 and VolanoMark 2.1.2, on two IBM PowerPC architectures, the RS64-III and the POWER3-II, and compare them to more traditional workloads as represented by selected benchmarks from SPECint20...