Energy efficient and performance efficient instruction fetch unit is a critical issue in modern processor design. Trace cache which stores dynamic basic-block stream can significantly improve performance efficiency. Conventional trace cache (CTC) usually adopts set associative structure which requires probing all the data ways in parallel such that only the output of the matched way is used, bu...

1 These notes are currently under review for publication by UCL Press Limited in the UK. Duplication of this draft is permitted by individuals for personal use only. Any other form of duplication or reproduction requires prior written permission of the author. This statement must be easily visible on the rst page of any reproduced copies. I would be happy to receive any comments you might have ...

1 These notes are currently under review for publication by UCL Press Limited in the UK. Duplication of this draft is permitted by individuals for personal use only. A n y other form of duplication or reproduction requires prior written permission of the author. This statement m ust be easily visible on the rst page of any reproduced copies. I would be happy to receive a n y comments you might ...

Abstract Aquatic ecosystems provide vital services, and macrophytes play a critical role in their functioning. Conceptual models indicate that shallow lakes, plants with different growth strategies are expected to inhabit contrasting habitats. For peat characterized by incohesive sediments, roles of forms, life-history environmental factors determining the occurrence aquatic vegetation remain u...

Caches are partitioned into subarrays for optimal timing In a set associative cache if the way holding the data is known before an access only subarrays for that way need to be accessed Reduction in cache switching activities results in energy savings In this paper we propose to extend the branch pre diction framework to enable way footprint prediction The next fetch address and its way footpri...

Not to be left out in the move to the next generation of RISC, MIPS Technologies (MTI) unveiled the design of the R10000, also known as T5. As the spiritual successor to the R4000, the new design will be the basis of high-end MIPS processors for some time, at least until 1997. By swapping superpipelining for an aggressively out-oforder superscalar design, the R10000 has the potential to deliver...

Address trace compression represents that the address data, which were generated from instruction fetch stage of microprocessor, can be retrieved for later observation and analysis. In h s paper, we present how to design and implement this real-time address trace compressor (RTATC), whch can be used to collect the address trace information of FPGA Prototyping system based on embedded microproce...

In current cache designs cache size and line size are often xed and determined by the spatial and temporal locality of benchmarks used to evaluate the targeted processors Stream bu er and large fetch size are two techniques that exploit spatial locality to hide memory latency In this paper we compare the e ectiveness of stream bu er and fetch size on media benchmarks We have presented a dynamic...

Various methods for value prediction have been proposed to overcome the limits imposed by data dependencies within programs. Using a value prediction scheme, an instruction's computed value is predicted during its fetch stage and forwarded to all dependent instructions to exploit parallelism. Value prediction schemes have focused on predicting the values generated by an instruction based on a l...

The microprocessor performance is increased by allowing multiple threads per clock cycle to issue instructions in simultaneous multithreading processors. Shared hardware resources are the key components of SMT processor performance. In SMT processors, impact to the performance will not be same among many hardware resources. To design an optimal hardware configuration for SMT processors, sensiti...