This article presents several grand challenges in the area of physical design for through-silicon via (TSV) based 3D ICs. Most of these issues are centered around TSVs, which are a new element of the 3D IC layout. Fundamental understanding of the electrical, mechanical, and thermal properties of TSVs is essential in successful physical design of TSV-based 3D ICs. Further investigation of the im...

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delayinsensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach p...

Complexity of design and testing are the major obstacle for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuit is accepted as an effective way to decrease complexity of design of asynchronous circuit. One of the popular pre-designed templates that most synthesis tools use it to synthesis QDI asynchronous circuit is Pre-Charged Full...

The integrated circuit revolution has impacted virtually all fields of engineering. The main driving force behind this revolution is Complementary Metal-Oxide Semiconductor (CMOS) transistor technology. As CMOS integrated circuit “chips” have come to dominate analog and digital electronics, introductory electronics courses in Electrical and Computer Engineering programs have evolved to place gr...

Power reduction is one of the biggest challenges in CMOS integrated circuit design. Optimization of power is inevitable in order to reduce package cost and extended battery life. As a switch tri-modal MTCMOS (Multi Threshold CMOS switch) can be considered as a low power solution for data retentive power gating applications. In MTCMOS, transistors with multiple threshold voltages are used in ord...

Multi-phase clocking methods are well known and widely used in high-performance integrated circuit design. Such a scheme allows for relaxation of timing constraints among disjoint partitions of the logic circuitry since lower frequency local clocking is required as compared to the system clock frequency at the cost of increased clock distribution network area. The disadvantage is that multiple ...

 The DSCH program is a logic editor and simulator designed by a research group under the leadership of E.Sicard, a professor of INSA of Toulouse . DSCH is used to validate the architecture of the logic circuit before the microelectronics design is started. DSCH provides a user-friendly environment for hierarchical logic design, and fast simulation with delay analysis, which allows the design a...

Robots are machines that sense, think, act and (more recently) communicate. Sensing, thinking, and communicating have all been greatly miniaturized as a consequence of continuous progress in integrated circuit design and manufacturing technology. More recent progress in MEMS (micro electro mechanical systems) now holds out promise for comparable miniaturization of the heretofore-retarded third ...