This paper presents a comprehensive analysis of the themal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which wi...

Novel compact expressions for propagation constant (γ) of SWCNT and bundled SWCNTs interconnect, in terms of physical parameters such as length, operating frequency and diameter of CNTs is proposed in this work. These simplified expressions enable physical insight and accurate estimation of signal attenuation level and its phase change at any length for a particular frequency. The proposed expr...

Process effects in deep-submicrometer geometries are expected to change the physical organization, or microarchitecture, of integrated circuits. The factor that is expected to primarily impact integrated circuit microarchitectures is increasing delays in interconnect. We believe that, to properly microarchitect integrated circuits in small process geometries, it is necessary to get as detailed ...

Interconnect effects that negatively impact performance, and compromise signal integrity are becoming more pronounced as technology moves deeper into sub-micron feature sizes, and designs are operated at higher frequencies. Many interconnect configurations and techniques have been proposed for a variety of domains (FPGA’s, ASIC’s, and networks...). In this work, we begin by investigating these ...

As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the density of integration many approaches have been proposed such as System on Chip (SoC), System in Package (SIP), and Networks on Chip (NoC)which all must address the interconnect issue address. Current approaches to So...

This paper addresses the interconnect problem of representation of logic networks in spatial dimensions. Interest to spatial interconnect is motivated by the advent in nanotechnologies and attempts to evaluate and explore the appropriate nanoscale architectures. It have been shown in our previous study that 3D logic network with target topology can be designed by replacing each elementary logic...

Electromigration is one of the most important reliability issues in semiconductor technology. Its complex character demands comprehensive physical modeling as basis for analysis. Simulation of electromigration induced interconnect failure focuses on the life-cycle of intrinsic voids, which consists of two distinct phases: void nucleation and void evolution. We present models for both phases as ...

In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the problem has been reported in the literature. SBWS is an iterative algorithm with guaranteed convergence to t...

This paper proposes the carbon nano structures particularly Carbon nanotube (CNT), Graphene Nanoribbon (GNR), with excellent electrical, thermal and mechanical properties making them an emerging alternative for future onchip interconnect applications. Analysis of CNT and GNR as onchip interconnect has been performed with the help of existing equivalent circuit model. Performance metrics such as...

This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is important that accurate physical information is used during high-level synthesis [1]. We propose a new power optimisation algorithm for RTlevel netlists. The optimisation performs simultaneously slicingtree structure-based flo...