A unified and consistent representation of logic gates at logic and circuit levels is described based on the subcircuit expansion approach. A dynamic-delay model is proposed for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering on the delay. It is shown that the approach provides near circuit-level accu...

We define an interpretation of modal languages with polyadic operators in modal languages that use monadic operators (diamonds) only. We also define a simulation operator which associates a logic Λ in the diamond language with each logic Λ in the language with polyadic modal connectives. We prove that this simulation operator transfers several useful properties of modal logics, such as finite/r...

Formulating a sound digital marketing strategy is a challenging task. A Web-enabled hybrid intelligent approach that combines online simulation, fuzzy logic, if-then rules and Web databases in support of digital marketing strategy formulation is proposed and presented in this paper. The effectiveness of the Web-based integrated system is assessed through case study evaluation work, with initial...

This paper describes various approaches for power analysis and minimization at the logic level including amongst others pattern independent probabilistic and symbolic simulation techniques for power estimation and low power techniques for state assignment logic re structuring logic decomposition technology mapping and pin ordering

Abettact SPLICE1 is a mixed-mode simulation program for large-scale integrated circuits. It performs concurrent electrical and logic simulation using event-driven selective-trace techniques. The electrical analysis uses a new algorithm , called Iterated Timing Analysis (ITA), which performs accurate electrical waveform analysis much faster than SPICEZ. The logic analysis features a new MOS-orie...

We show that Pauly’s Coalition Logic can be embedded into a richer normal modal logic that we call Normal Simulation of Coalition Logic (NCL). We establish that the latter is strictly more expressive than the former by proving that it is NEXPTIME complete in the case of at least two agents.

Hardware Description Languages (HDL) like VHDL are widely used to design and simulate with programmable logic devices. Simulation of very large scale integrated digital systems (VLSI) is of great importance as it assures system correctness and maximizes system performance ([4], [5], [9]). The utilization of parallel simulation introduces the problem of how to partition the logic gates and syste...