In this paper, design of low power, 9-bit pipeline ADC architecture is introduced .A pipeline ADC architecture has a 3-stage pipeline ADC with 3-bit flash ADC followed by a 3-bit DAC at each stage. A novel approach to design a 3-bit ADC is implemented; this design offers less number of comparator and low power consumption with less circuit complexity based on this idea a 9-bit ADC is simulated ...

This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization achieve good frame error rate (FER) performance with very low message precision. For message-passing according a flooding schedule, parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 L...

This paper is devoted to VLSI technology for high security purpose. Textual information is embedded in to an audio using LSB coding and it is encrypted and decrypted by Steganography algorithm. Low bit encoding or Least Significant Bit (LSB) encoding technique is proposed to encode the least significant bit of a host file with a bit of the Steganography data. This method assumes that this alter...