This paper presents a simple system consisting of the FPGA core, network protocol and Linux kernel driver, aimed on efficient transmission of acquired data from the low resources FPGA equipped with Ethernet PHY to the embedded system, responsible for preprocessing of those data and sending them further via standard network links. The system has been optimized regarding the memory and logic cons...

In a cache-coherent, shared-memory multiprocessor system, data consistency among cached copies can be delayed until synchronization points under relaxed memory consistency models. Some protocols called delayed consistency protocols take advantage of this flexibility to reduce cache miss rates and memory traffic. However, they are very complex and validating their correctness, even at the behavi...

As the number of cores and functionalities integrated in embedded devices increases, the amount of memory used on these devices also increases, justifying the development of memory architectures presenting scalability, low energy consumption and low latency. To implement memory solutions, most works adopting NoC-based MPSoCs only employ basic communication services, such as send/receive, withou...

The granularity of sharing is one of the key components that a ect the performance in distributed shared memory DSM systems Providing only one or two xed size granu larities to the user may not result in an e cient use of resources Providing an arbitrarily variable granularity increases hardware and or software overheads Moreover its e cient implementation requires the user to provide some info...

The immediate snapshot complexes were introduced as combinatorial models for the protocol complexes in the context of theoretical distributed computing. In the previous work we have developed a formal language of witness structures in order to define and to analyze these complexes. In this paper, we study topology of immediate snapshot complexes. It is known that these complexes are always pure...

In this paper, we show how a multiprocessor can be physically detached from its main memory using commercially available secondary cache controllers and high-speed ber optic links organized as a star network. The implementation connects up to eight Motorola 88110 processors to a single memory controller/directory cache. The memory access latency in this arrangement is lower. Communication time ...

the aim of the study was to find whether there is an association between subjective memory complaint and memory impairment and probable underlying psychological conditions. a total of 90 patients with subjective memory complaint enrolled in this study. short history and demographic information were obtained and then the patients underwent memory and mental health assessments, using wechsler mem...

This paper proposes a variant of the recently reported pool mining approach and provides reduction in energy that is consumed by blockchain consensus protocol. The novelty proposed architecture lies employment an innovative cryptographic puzzle based on stream ciphering. enables flexibility setting difficulty parameter protocol, allows for separation memory resources are required solving. high ...

The compute requirements associated with the TCP/IP protocol suite have been previously studied by a number of researchers. However, the recently developed 10-Gigabit Networks such as 10Gigabit Ethernet and InfiniBand have added a new dimension of complexity to this problem, Memory Traffic. While there have been previous studies which show the implications of the memory traffic bottleneck, to t...