This article describes the implementation in hardware of an Artificial Neural Network with an embedded Microprocessor in a FPGA. The implementation of a Neural Network in hardware can be desired to benefit from its distributed processing capacity or to avoid using a personal computer attached to each implementation. The relevance of implementing it in a FPGA comes from its flexibility, low powe...

This paper presents the PACE partitioning algorithm which is used in the LYCOS co-synthesis system for partitioning control/dataaow graphs into hardware-and software parts. The algorithm is a dynamic programming algorithm which solves both the problem of minimizing system execution time with a hardware area constraint and the problem of minimizing hardware area with a system execution time cons...

Reducing switching activity would significantly reduce power consumption of a processor chip. In this paper, we present two novel techniques, Gray code addressing and Cold scheduling, for reducing switching activity on high performance processors. We use Gray code which has only one-bit different in conseuctive number for addressing. Due to locality of program execution, Gray code addressing ca...

v Acknowledgements vii Executive Summary ix 1 Background and Introduction 1 1.1 Goals of Model-Based Verification Efforts 1 1.2 Structure and Content of the Report 2 2 Model-Based Verification 3 2.1 The Model-Based Verification Paradigm 3 2.2 Context and Related Work 6 2.3 Model-Based Verification in Software Upgrades 6 3 Technical Aspects of Model-Based Verification 9 3.1 Models 9 3.2 Formalis...

We present an optoelectronic-VLSI system that integrates complementary metal-oxide semiconductory multiple-quantum-well smart pixels for high-throughput computation and signal processing. The system uses 5 3 10 cellular smart-pixel arrays with intrachip electrical mesh interconnections and interchip optical point-to-point interconnections. Each smart pixel is a fine grain microprocessor that ex...

As the device size continues to shrink and circuit complexity continues to grow, power has become the limiting factor in today’s microprocessor design. Since the power dissipation is a function of many variables with uncertainty, the most accurate representation of chip power or macro power is a statistical distribution subject to process and workload variation, instead of a single number for t...

It becomes a trend that microprocessor companies are adding more and more parallelism on a chip to increase performance per chip. At the fine granularity level, vector instruction sets are added. While at the coarse granularity level, multiple cores are put on the same chip. This trend presents a challenge for application developers as well for compiler developers: how to exploit the power of t...

Variation is the deviation from intended or designed values for a structure or circuit parameter of concern. The electrical performance of microprocessors or other integrated circuits are impacted by two sources of variation. Environmental factors are those which arise during the operation of a circuit, and include variations in power supply, switching activity, and temperature of the chip or a...

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used for various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to th...

The Data-Intensive Architecture (DIVA) system incorporates Processing-In-Memory (PIM) chips as smart-memory coprocessors to a microprocessor. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications. A key capability of this architecture is the support of parallel single-precision floating-point operation...