We show basic facts about dp-minimal ordered structures. The main results are: dp-minimal groups are abelian-by-finite-exponent, in a divisible ordered dp-minimal group, any infinite set has non-empty interior, and any theory of pure tree is dp-minimal.

Among the various proposals for defeasible reasoning for description logics, Rational Closure, a procedure originally defined for propositional logic, turns out to have a number of desirable properties. Not only it is computationally feasible, but it can also be implemented using existing classical reasoners. One of its drawbacks is that it can be seen as too weak from the inferential point of ...

you need to be sure that this type of architecture makes sense. Certainly, if you already have one or both of the desired applications running on their own, combining the functionality by integrating the two processors is a logical solution. This type of architecture also provides for a logical division of functionality, including letting the DSP focus on the key algorithms. The DSP of course i...

Binary Erasure Channels (BEC) can be used to model transmission erasures, for example, symbol erasures in TCP’s link layer and network layer. In order to tackle the erasures incurred, the transceiver system relies on retransmission of the lost packets using acknowledgment and repeat request based schemes. This missing packet information or acknowledgments can be conveyed by the receiver to the ...

In this paper, Continuous Phase Modulation (CPM) is investigated. We employ the decomposed CPM model where the model is decomposed into a Continuous Phase Encoder (CPE) and a Memoryless Modulator (MM). This allows us to concentrate on the encoding aspects without interference from the modulator. By designing a convolutional channel encoder (CE), to operate over the same algebra as the CPE, the ...

An Artificial Neural Network-based error compensation method is proposed for improving the accuracy of resolver-based 16-bit encoders by compensating for their respective systematic error profiles. The error compensation procedure, for a particular encoder, involves obtaining its error profile by calibrating it on a precision rotary table, training the neural network by using a part of this dat...

This paper proposes a novel VLSI architecture for Video Encoder, which processes high resolution video sequences at real time rates. The architecture has been realized using Verilog and implemented on an Xilinx XUPVP30 FPGA. The gate count of the implementation is approximately 800,000 including an output FIFO of size 128 K bits. It can process 1600x1200 pixels color motion pictures in 4:2:0 fo...

Abstract An important feature of a dynamic game is its monitoring structure namely, what the players effectively see from the played actions. We consider games with arbitrary monitoring structures. One of the purposes of this paper is to know to what extent an encoder, who perfectly observes the played actions and sends a complementary public signal to the players, can establish perfect monitor...

What do auto-encoders learn about the underlying data generating distribution? Recent work suggests that some auto-encoder variants do a good job of capturing the local manifold structure of data. This paper clarifies some of these previous observations by showing that minimizing a particular form of regularized reconstruction error yields a reconstruction function that locally characterizes th...