In order to protect the security of network data, a high speed chip module for encrypting and decrypting of network data packet is designed. The chip module is oriented for internet information security SOC (System on Chip) design. During the design process, AES (Advanced Encryption Standard) and 3DES (Data Encryption Standard) encryption algorithm are adopted to protect the security of network...

let r be a ring, m a right r-module and (s,≤) a strictly ordered monoid. in this paper we will show that if (s,≤) is a strictly ordered monoid satisfying the condition that 0 ≤ s for all s ∈ s, then the module [[ms,≤]] of generalized power series is a uniserial right [[rs,≤]] ]]-module if and only if m is a simple right r-module and s is a chain monoid.

Let $A$ be a Banach algebra and $E$ be a Banach $A$-bimodule then $S = A oplus E$, the $l^1$-direct sum of $A$ and $E$ becomes a module extension Banach algebra when equipped with the algebras product $(a,x).(a^prime,x^prime)= (aa^prime, a.x^prime+ x.a^prime)$. In this paper, we investigate $triangle$-amenability for these Banach algebras and we show that for discrete inverse semigroup $S$ with...

In this paper, we present an iterative framework to solve module selection problem under resource, latency, and power constraints. The framework associates a utility measure with each module. This measurement reflects the usefulness of the module for a given a design goal. Using modules with high utility values will result in superior designs. We propose a heuristic which iteratively perturbs m...