We present a gate delay model of CMOS logic gates driving a CRC load for deep sub-micron technology. Our approach is to replace series-parallel connected MOSFETs to an equivalent MOSFET and calculate the output waveform by an analytically derived formula. We present a MOSFET drain current model improved from the -th power law MOSFET model to represent the characteristic of the equivalent invert...

Received Jan 9, 2018 Revised Mar 2, 2018 Accepted Mar 18, 2018 There is a growing demand of miniaturization of the electronics world. A brief discussion for simulating and fabrication of the MOSFET based pressure sensor in nanoscale is being reviewed in this paper. Aim of this paper is to collect all the scaling challenges and their solutions together to make understanding the facts of the MOSF...

The limits on scaling suggest the technology advancement for the solid-state devices. The double-gate (DG) MOSFET has emerged as an alternative device structure due to the certain significant advantages, i.e. increase in mobility, ideal sub-threshold slope, higher drain current, reduced power consumption and screening of source end of the channel by drain electric field (due to proximity to the...

We report on a GaN metal-oxide-semiconductor field-effect-transistor (MOSFET) using atomic-layer-deposited (ALD) Al2O3 as the gate dielectric. Compared to a GaN metal-semiconductor field-effect-transistor (MESFET) of similar design, the MOSFET exhibits several orders of magnitude lower gate leakage and near three times higher channel current. This implies that the ALD Al2O3/GaN interface is of ...

Received April 27, 2012 Revised May 14, 2012 Accepted May 26, 2012 Application of symmetric double gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple process simulation has been developed to reduce the...

The fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation is the first model for circuit simulation based on a complete surface-potential description. HiSIM-SOI solves the surface potentials at all three SOI-surfaces perpendicular to the channel surface self-consistently. Besides verification against measured I-V characteristics, HiSIM-SOI is also verified with a 1/f noise analysis, ...

In this research, the probabilistic model of the random variations in nanoscale MOSFET’s high frequency performance defined in term of variation in gate capacitance, has been proposed. Both random dopant fluctuation and process variation effects which are the major causes of the MOSFET’s high frequency characteristic variations have been taken into account. The nanoscale MOSFET equation has bee...

The 7th-order Bessel filter presented in this paper has an edge frequency that is continuously tunable from 4.5 MHz up to 10 MHz. It was fabricated with the 0.6-micron CMOS process by AMS, covers a chip area of 0.24 mm2, and consumes 49 mW from a 3.3-V supply. The SNR at −40 dB of harmonic distortion is between 48 dB and 50 dB over the whole tuning range. The comparatively low power consumption...

Scaling of metal-oxide-semiconductor transistors to smaller dimensions has been a key driving force in the IC industry. This work analysis the gate leakage current behavior of nano scale MOSFET based on TCAD simulation. The Sentaurus Simulator simulates the high-k gate stack structure of N-MOSFET for analysis purpose. The impact of interfacial oxide thickness on the gate tunneling current has b...

A model for the simulation of the electron energy distribution in nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET) devices, using a kinetic simulation technique, is implemented. The convective scheme (CS), a method of characteristics, is an accurate method of solving the Boltzmann transport equation, a nonlinear integrodifferential equation, for the distribution of electrons...