This work faces the problem of the HW/SW co-design of dedicated systems based on heterogeneous multi multi-core processor architectures. In particular, it proposes an extension of a previous system-level design space exploration (DSE) approach able to suggest to the designer an HW/SW partitioning of the system specification and a mapping of the partitioned entities onto an automatically selecte...

Programming and debugging of Multi-Core systems is hard. We present a Fast Prototyping tool that can generate a complete Multi-core system targeted for single-chip FPGA solutions, including software synthesis, reducing design time from weeks to a couple of hours. The system is NoC-based and configured using an XML-file. By selecting the number and type of processors for each node, both homoand ...

Single-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention but developing applications for such architectures is not an easy task due to the lack of appropriate tools and programming models. We present the design of a runtime syste...

ARCHITECTURAL AND COMPILER MECHANISMS FOR ACCELERATING SINGLE THREAD APPLICATIONS ON MULTICORE PROCESSORS

c © 2007 by John von Neumann Institute for Computing Permission to make digital or hard copies of portions of this work for personal or classroom use is granted provided that the copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise requires prior specific permission by the publisher ment...

The aim of rapid development of communication systems is to automate the process of transforming the high level description of a protocol into hardware and software that would implement the actual system. This paper describes a methodology used to implement medium access protocols based on a microprocessor core and a general parameterized architecture which contains configurable hardware blocks...

Heterogeneous multicore architectures appear to be a promising solution to the ever-increasing computational demands of applications in embedded as well as high-performance computing domains. Nevertheless, inefficient application partitioning for such systems may result in a considerable reduction in the anticipated performance improvement. Consequently, proper mechanisms are required to evalua...