We present n-valued rst-order logics with a purely proba-bilistic semantics. We then introduce a new probabilistic semantics of n-valued rst-order logics that lies between the purely probabilistic semantics and the truth-functional semantics of the n-valued Lukasiewicz logics Ln. Within this semantics, closed formulas of classical rst-order logics that are logically equivalent in the classical ...

This paper presents an algorithm based on an artificial immune system to minimize the multiple-valued logic (MVL) functions. In the proposed algorithm, the length of antibody (solution) is adaptive in order to reduce the computational complexity. The affinity function is designed to consist of two metrics (correctness and optimality) so that the average number of product terms in the solution c...

We propose a minimization algorithm that combines cost tables and simulated annealing. Unlike other minimization procedures that use cost tables, our method does not rely on the enumeration of all minterms, it works directly with the expression (a sum of product terms). We tested our method with a cost table obtained from current mode CMOS. The algorithm can be readily adapted to any other tech...

We analyze the performance of various heuristic algorithms for minimizing realizations of multiple-valued functions by the newly developed CCD 191 and CMOS [W] programmable logic arrays. The functions realized by such PLA's are in sum-of-products form, where sum is ordinary addition truncated to the highest logic value, and where product represents the MIN operation on functions of the input va...

A universal literal is a single-variable function and has an ability to manipulate more information than a set lateral. The array size therefore could be eliminated b y using universal literal generators (ULGs for short) in programmable logic arrays (PLAs), compared to PLAs with set literals. This paper discusses what operator is the most suitable in the term of eliminating the array size. We f...

Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI) using binary logic is reaching a point where most of the silicon area is occupied with interconnecting lines among devices on the chip, which represents a drawback of the approach. First implication of the high wiring complexity is increased packing complexity with increased number of pins (in today's VLSI ...