We propose a p-i-n diode embedded parallel triple microring resonator (MRR) configuration to simultaneously realize optical OR and AND, or NAND NOR logic gates using bias-assisted carrier injection mechanism. The applied bias on the rings induces refractive index change in intrinsic region through bandfilling, bandgap shrinkage free absorption effects, leading intensity variation at output port...

Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as an important threat to the reliability of synchronous digital circuits. To protect circuits from these timing errors, designers typically use a conservative timing margin, which leads to operational inefficiency. Existing adaptive approaches reduce such conservative margins by predicting the timi...

In this paper we investigate-bit serial addition in the context of feed-forward linear threshold gate based networks. We show that two n-bit operands can be added in 2d p n e overall delay with a feed-forward network constructed with d p n e + 1 linear threshold gates and 1 2 (5d p n e 2 + 9d p n e) + 2 latches. The maximum weight value is 2 d p n e and the maximum fan-in is 3d p n e+1. We also...

<span>This paper presents the FPGA-based implementation of compact montgomery modular multiplier (MMM). MMM serves as a building block commonly required in security protocols relying on public key encryption. The proposed design is intended for hardware applications lightweight cryptographic modules that utilized system chip (SoC) and internet things (IoT) devices. modification structure ...

This paper presents a high-speed method for computing elementary functions using parallel table lookups and multi-operand addition. Increasing the number of tables and inputs to the multi-operand adder significantly reduces the amount of memory required. Symmetry and leading zeros in the table coefficients are used to reduce the amount of memory even further. This method has a closed-form solut...

A novel one-directional pass-through array for the computation of integer greatest common divisor is designed and implemented on Atmel FPGA. The design is based on the plus-minus GCD algorithm and works in LSB pipelined manner. In contrast with previous designs, the length of the new array is independent of the length of the operands: arbitrary long integers can be processed in multiple passes....

We apply genetic programming techniques to the ‘shepherding’ problem, in which a group of one type of animal (sheep dogs) attempts to control the movements of a second group of animals (sheep) obeying flocking behavior. Our genetic programming algorithm evolves an expression tree that governs the movements of each dog. The operands of the tree are hand-selected features of the simulation enviro...

SequenceL is a concise, high-level language with a simple semantic that provides for the automatic derivation of many iterative and all parallel control structures. The semantic repeatedly applies a “Normalize-Transpose-Distribute” operation to functions and operators until base cases are discovered. Base cases include the grounding of variables and the application of built-in operators to oper...

This paper presents a scalable architecture for the computation of modular multiplication, based on the Montgomery multiplication (MM) algorithm. A word-based version of MM is presented and used to explain the main concepts in the hardware design. The proposed multiplier is able to work with any precision of the input operands, limited only by memory or control constraints. Its architecture giv...

We describe a variant of a domain decomposi tion method proposed by Gleicher and Kass for in tersecting and trimming parametric surfaces In stead of using interval arithmetic to guide the de composition the variant described here uses a ne arithmetic a tool recently proposed for range analy sis A ne arithmetic is similar to standard interval arithmetic but takes into account correlations be twe...