We propose a low-memory-bandwidth, high-efficiency VLSI architecture for 60-k word real-time continuous speech recognition. Our architecture includes a cache architecture using the locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, a parallel Gaussian Mixture Model (GMM) architecture based on the mixture level and frame level, a parallel ...

This paper presents a processor array design for flexible approximate string matching. Initially, a sequential algorithm is discussed which consists of two phases, i.e. preprocessing and searching. Then, starting from the computational schedule of the searching phase a parallel architecture is derived. Further, the preprocessing phase is also accomodated onto the same architecture. Key-Words: A...

We present the PPOST-architecture (Persistent Parallel Object Store) for main-memory database systems on parallel computers, that is suited for applications with challenging performance requirements. The architecture takes full advantage of parallelism, large main memories and fast switching networks. An important property of this architecture is its excellent scaling behavior.

the increasing diversity in packet-processing applications together with the rapid increase in channel bandwidth has brought about greater complexity in communication protocols. also influenced by these factors is the computational load for packet-processing engines, demanding high performance microprocessor designs as an indispensable solution. this paper reports on extensive simulation experi...

An SIMD massively parallel computer has to compete with workstations and parallel systems based on off-the-shelf microprocessor. This report motivate the choice for the development of a SIMD massively parallel architecture for image processing focusing on the constraints under which the architecture can succesfully compete with available sequential systems. The correct design methodology is als...

Abstract A lifting-based VLSI architecture for twodimensional discrete wavelet transform (2-D DWT) for 5/3 and 9/7 algorithms, called, pipelined intermediate architecture was proposed by Ibrahim et al., which aim at reducing power consumption of the overlapped external memory access without using the expensive line-buffer. In this paper, we explore parallelism in order to best meet real-time ap...

This paper presents three energy-efficient methods for searching and filtering streamed data on a fine-grained manycore processor array: parallel, serial, and all-in-one. All three architectures aim to provide programmable flexibility with low energy consumption. Experimental results show that for one keyword search, the parallel and serial architectures consume 2× less energy per workload than...

The Proteus language is a wide-spectrum parallel programming notation that supports the expression of both high-level architecture-independent speciications and lower-level architecture-speciic implementations. A methodology based on successive reenement and interactive experimentation supports the development of parallel algorithms from speciication to various eecient architecture-dependent im...

Numerical validation of computed results in scienti c computation is always an essential problem as well on sequential architecture as on parallel architecture. The probabilistic approach is the only one that allows to estimate the round-o error propagation of the oating point arithmetic on computers. We begin by recalling the basics of the CESTAC method (Contrôle et Estimation STochastique des...